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LXT972A
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
Datasheet
The LXT972A is an IEEE compliant Fast Ethernet PHY Transceiver that directly supports both 100BASE-TX and 10BASE-T applications. It provides a Media Independent Interface (MII) for easy attachment to 10/100 Media Access Controllers (MACs). This document also supports the LXT972. The LXT972A supports full-duplex operation at 10Mbps and 100Mbps. Its operating condition can be set using auto-negotiation, parallel detection, or manual control. The LXT972A is fabricated with an advanced CMOS process and requires only a single 3.3V power supply.
Applications
s
Combination 10BASE-T/100BASE-TX Network Interface Cards (NICs)
s s
10/100 PCMCIA Cards Cable Modems and Set-Top Boxes
Product Features
s s s s s s
3.3V Operation. Low power consumption (300 mW typical). 10BASE-T and 100BASE-TX using a single RJ-45 connection. Supports auto-negotiation and parallel detection. MII interface with extended register capability. Robust baseline wander correction performance.
s s s s
Standard CSMA/CD or full-duplex operation. Configurable via MDIO serial port or hardware control pins. Integrated, programmable LED drivers. 64-pin Low-profile Quad Flat Package (LQFP). -- LXT972ALC - Commercial (0 to 70C ambient).
As of January 15, 2001, this document replaces the Level One document LXT972A 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet.
Order Number: 249186-002 January 2001
Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT972A may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners.
Datasheet
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet -- LXT972A
Contents
1.0 2.0 3.0 Pin Assignments ............................................................................................................10 Signal Descriptions........................................................................................................13 Functional Description ..................................................................................................16 3.1 Introduction..........................................................................................................16 3.1.1 Comprehensive Functionality .................................................................16 3.1.2 OSPTM Architecture ................................................................................16 Network Media / Protocol Support.......................................................................17 3.2.1 10/100 Network Interface .......................................................................17 3.2.1.1 Twisted-Pair Interface ...............................................................17 3.2.1.2 Fault Detection and Reporting...................................................17 3.2.2 MII Data Interface...................................................................................18 3.2.3 Configuration Management Interface .....................................................18 3.2.3.1 MDIO Management Interface ....................................................18 3.2.3.2 MII Interrupts .............................................................................19 3.2.3.3 Hardware Control Interface .......................................................19 Operating Requirements .....................................................................................20 3.3.1 Power Requirements..............................................................................20 3.3.2 Clock Requirements ...............................................................................20 3.3.2.1 External Crystal/Oscillator .........................................................20 3.3.2.2 MDIO Clock ...............................................................................20 Initialization..........................................................................................................21 3.4.1 MDIO Control Mode ...............................................................................21 3.4.2 Hardware Control Mode .........................................................................21 3.4.3 Reduced Power Modes ..........................................................................22 3.4.3.1 Hardware Power Down .............................................................22 3.4.3.2 Software Power Down ...............................................................22 3.4.4 Reset ......................................................................................................23 3.4.5 Hardware Configuration Settings ...........................................................23 Establishing Link .................................................................................................24 3.5.1 Auto-Negotiation.....................................................................................24 3.5.1.1 Base Page Exchange................................................................24 3.5.1.2 Next Page Exchange.................................................................24 3.5.1.3 Controlling Auto-Negotiation .....................................................25 3.5.2 Parallel Detection ...................................................................................25 MII Operation.......................................................................................................25 3.6.1 MII Clocks...............................................................................................26 3.6.2 Transmit Enable .....................................................................................26 3.6.3 Receive Data Valid.................................................................................26 3.6.4 Carrier Sense .........................................................................................26 3.6.5 Error Signals...........................................................................................26 3.6.6 Collision..................................................................................................26 3.6.7 Loopback................................................................................................28 3.6.7.1 Operational Loopback ...............................................................28 3.6.7.2 Test Loopback ...........................................................................28 100Mbps Operation.............................................................................................29
3.2
3.3
3.4
3.5
3.6
3.7
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LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
3.8
3.9
3.10
100BASE-X Network Operations ........................................................... 29 Collision Indication ................................................................................. 31 100BASE-X Protocol Sublayer Operations ............................................ 31 3.7.3.1 PCS Sublayer............................................................................ 31 3.7.3.2 PMA Sublayer ........................................................................... 34 3.7.3.3 Twisted-Pair PMD Sublayer ...................................................... 34 10Mbps Operation............................................................................................... 35 3.8.1 10T Preamble Handling ......................................................................... 35 3.8.2 10T Carrier Sense.................................................................................. 36 3.8.3 10T Dribble Bits...................................................................................... 36 3.8.4 10T Link Integrity Test............................................................................ 36 3.8.4.1 Link Failure................................................................................ 36 3.8.5 10T SQE (Heartbeat) ............................................................................. 36 3.8.6 10T Jabber ............................................................................................. 36 3.8.7 10T Polarity Correction .......................................................................... 37 Monitoring Operations......................................................................................... 37 3.9.1 Monitoring Auto-Negotiation................................................................... 37 3.9.1.1 Monitoring Next Page Exchange............................................... 37 3.9.2 LED Functions........................................................................................ 37 3.9.2.1 LED Pulse Stretching ................................................................ 38 Boundary Scan (JTAG1149.1) Functions ........................................................... 38 3.10.1 Boundary Scan Interface........................................................................ 38 3.10.2 State Machine ....................................................................................... 39 3.10.3 Instruction Register ................................................................................ 39 3.10.4 Boundary Scan Register (BSR).............................................................. 39 Magnetics Information......................................................................................... 40 Typical Twisted-Pair Interface............................................................................. 40 Electrical Parameters .......................................................................................... 44 Timing Diagrams ................................................................................................. 47
3.7.1 3.7.2 3.7.3
4.0
Application Information................................................................................................. 40 4.1 4.2
5.0
Test Specifications ........................................................................................................ 44 5.1 5.2
6.0 7.0
Register Definitions ....................................................................................................... 55 Package Specification ................................................................................................... 70
4
Datasheet
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet -- LXT972A
Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 LXT972A Block Diagram ....................................................................................... 9 LXT972A 64-Pin LQFP Assignments ..................................................................10 Management Interface Read Frame Structure ...................................................19 Management Interface Write Frame Structure ...................................................19 Interrupt Logic ....................................................................................................20 Initialization Sequence .......................................................................................22 Hardware Configuration Settings .......................................................................23 Link Establishment Overview .............................................................................25 10BASE-T Clocking ............................................................................................27 100BASE-X Clocking .........................................................................................27 Link Down Clock Transition ................................................................................27 Loopback Paths ..................................................................................................28 100BASE-X Frame Format ................................................................................29 100BASE-TX Data Path .....................................................................................29 100BASE-TX Reception with no Errors ..............................................................30 100BASE-TX Reception with Invalid Symbol .....................................................30 100BASE-TX Transmission with no Errors .......................................................31 100BASE-TX Transmission with Collision .........................................................31 Protocol Sublayers .............................................................................................32 LED Pulse Stretching .........................................................................................38 Typical Twisted-Pair Interface - Switch ...............................................................41 Typical Twisted-Pair Interface - NIC ...................................................................42 Typical MII Interface ...........................................................................................43 100BASE-TX Receive Timing - 4B Mode ...........................................................47 100BASE-TX Transmit Timing - 4B Mode ..........................................................48 10BASE-T Receive Timing .................................................................................49 10BASE-T Transmit Timing ................................................................................50 10BASE-T Jabber and Unjabber Timing ............................................................51 10BASE-T SQE (Heartbeat) Timing ...................................................................51 Auto Negotiation and Fast Link Pulse Timing ....................................................52 Fast Link Pulse Timing .......................................................................................52 MDIO Input Timing .............................................................................................53 MDIO Output Timing ..........................................................................................53 Power-Up Timing ................................................................................................54 RESET Pulse Width and Recovery Timing ........................................................54 PHY Identifier Bit Mapping .................................................................................60 LXT972A LQFP Package Specifications ............................................................70
Tables
1 2 3 4 5 6 7 8 LQFP Numeric Pin List.......................................................................................11 LXT972A MII Signal Descriptions........................................................................13 LXT972A Network Interface Signal Descriptions ................................................14 LXT972A Miscellaneous Signal Descriptions......................................................14 LXT972A Power Supply Signal Descriptions ......................................................15 LXT972A JTAG Test Signal Descriptions ...........................................................15 LXT972A LED Signal Descriptions......................................................................15 Hardware Configuration Settings ........................................................................24
Datasheet
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LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
Carrier Sense, Loopback, and Collision Conditions............................................ 28 4B/5B Coding ...................................................................................................... 33 BSR Mode of Operation ...................................................................................... 39 Supported JTAG Instructions .............................................................................. 39 Device ID Register .............................................................................................. 39 Magnetics Requirements .................................................................................... 40 RJ-45 Pin Comparison of NIC and Switch Twisted-Pair Interfaces .................... 40 Absolute Maximum Ratings ................................................................................ 44 Operating Conditions .......................................................................................... 44 Digital I/O Characteristics 1................................................................................. 45 Digital I/O Characteristics - MII Pins ................................................................... 45 I/O Characteristics - REFCLK/XI and XO Pins.................................................... 45 I/O Characteristics - LED/CFG Pins.................................................................... 45 100BASE-TX Transceiver Characteristics .......................................................... 46 10BASE-T Transceiver Characteristics............................................................... 46 10BASE-T Link Integrity Timing Characteristics ................................................. 46 100BASE-TX Receive Timing Parameters - 4B Mode........................................ 47 100BASE-TX Transmit Timing Parameters - 4B Mode ....................................... 48 10BASE-T Receive Timing Parameters.............................................................. 49 10BASE-T Transmit Timing Parameters............................................................. 50 10BASE-T Jabber and Unjabber Timing Parameters ......................................... 51 10BASE-T SQE Timing Parameters ................................................................... 51 Auto Negotiation and Fast Link Pulse Timing Parameters.................................. 52 MDIO Timing Parameters ................................................................................... 53 Power-Up Timing Parameters............................................................................ 54 RESET Pulse Width and Recovery Timing Parameters .................................... 54 Register Set ........................................................................................................ 55 Register Bit Map.................................................................................................. 56 Control Register (Address 0)............................................................................... 58 MII Status Register #1 (Address 1) ..................................................................... 58 PHY Identification Register 1 (Address 2)........................................................... 59 PHY Identification Register 2 (Address 3)........................................................... 60 Auto Negotiation Advertisement Register (Address 4)........................................ 61 Auto Negotiation Link Partner Base Page Ability Register (Address 5) .............. 62 Auto Negotiation Expansion (Address 6) ............................................................ 63 Auto Negotiation Next Page Transmit Register (Address 7) ............................... 63 Auto Negotiation Link Partner Next Page Receive Register (Address 8) ........... 64 Configuration Register (Address 16, Hex 10) ..................................................... 64 Status Register #2 (Address 17) ......................................................................... 65 Interrupt Enable Register (Address 18)............................................................... 66 Interrupt Status Register (Address 19, Hex 13) .................................................. 66 LED Configuration Register (Address 20, Hex 14) ............................................. 68 Transmit Control Register #2 (Address 30)......................................................... 69
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Datasheet
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet -- LXT972A
Revision History
Revision 002 Date January 2001 Description Clock Requirements: Modified language under Clock Requirements heading. I/O Characteristics REFCLK (table): Changed values for Input Clock Duty Cycle under Min from 40 to 35 and under Max from 60 to 65.
Datasheet
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3.3V Dual-Speed Fast Ethernet Transceiver Datasheet -- LXT972A
Figure 1. LXT972A Block Diagram
RESET ADDR0 MDIO MDC MDINT MDDIS TX_EN TX PCS TXD<3:0> TX_ER TX_CLK Parallel/Serial Converter Management / Mode Select Logic Pwr Supply Register Set Clock Generator
VCC GND PWRDWN REFCLK TxSLEW<1:0>
Manchester 10 Encoder Scrambler 100 & Encoder Auto Negotiation Register Set
OSPTM
Pulse Shaper
TP Driver
+ TP Out TPOP TPON
LED/CFG<3:1> Collision Detect
JTAG
OSPTM
COL Clock Generator Media Select Adaptive EQ with Baseline Wander Cancellation
+
100TX
TDI, TDO, TMS, TCK, TRST
RX_CLK RXD<3:0> RXDV CRS RX_ER RX PCS Carrier Sense Data Valid Error Detect Serial-toParallel Converter
10
Manchester Decoder TPIP
OSPTM
Slicer
TP In
TPIN
Decoder & 100 Descrambler
+
10BT
-
Datasheet
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LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
1.0
Pin Assignments
Figure 2. LXT972A 64-Pin LQFP Assignments MDINT CRS COL GND TXD3 TXD2 TXD1 TXD0 TX_EN TX_CLK TX_ER RX_ER RX_CLK VCCD GND RX_DV 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
REFCLK/XI XO MDDIS RESET TXSLEW0 TXSLEW1 GND VCCIO N/C N/C GND ADDR0 GND GND GND GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Part # LOT # FPO #
LXT972A XX XXXXXX XXXXXXXX
Rev #
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
RXD0 RXD1 RXD2 RXD3 N/C MDC MDIO GND VCCIO PWRDWN LED/CFG1 LED/CFG2 LED/CFG3 TEST1 TEST0 PAUSE
Package Topside Markings Marking Part # Rev # Lot # FPO # Definition LXT972A is the unique identifier for this product family. Identifies the particular silicon "stepping" (Refer to Specification Update for additional stepping information.) Identifies the batch. Identifies the Finish Process Order.
10
RBIAS GND TPOP TPON VCCA VCCA TPIP TPIN GND GND TDI TDO TMS TCK TRST GND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Datasheet
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet -- LXT972A
Table 1.
LQFP Numeric Pin List
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Symbol REFCLK/XI XO MDDIS RESET TxSLEW0 TxSLEW1 GND VCCIO N/C N/C GND ADDR0 GND GND GND GND RBIAS GND TPOP TPON VCCA VCCA TPIP TPIN GND GND TDI TDO TMS TCK TRST GND PAUSE TEST0 TEST1 LED/CFG3 Type Input Output Input Input Input Input - - - - - Input - - - - Analog Input - Output Output - - Input Input - - Input Output Input Input Input - Input Input Input I/O Reference for Full Description Table 4 on page 14 Table 4 on page 14 Table 2 on page 13 Table 4 on page 14 Table 4 on page 14 Table 4 on page 14 Table 5 on page 15 Table 5 on page 15 Table 4 on page 14 Table 4 on page 14 Table 5 on page 15 Table 4 on page 14 Table 5 on page 15 Table 5 on page 15 Table 5 on page 15 Table 5 on page 15 Table 4 on page 14 Table 5 on page 15 Table 3 on page 14 Table 3 on page 14 Table 5 on page 15 Table 5 on page 15 Table 3 on page 14 Table 3 on page 14 Table 5 on page 15 Table 5 on page 15 Table 6 on page 15 Table 6 on page 15 Table 6 on page 15 Table 6 on page 15 Table 6 on page 15 Table 5 on page 15 Table 4 on page 14 Table 4 on page 14 Table 4 on page 14 Table 7 on page 15
Datasheet
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LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
Table 1.
LQFP Numeric Pin List (Continued)
Pin 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Symbol LED/CFG2 LED/CFG1 PWRDWN VCCIO GND MDIO MDC N/C RXD3 RXD2 RXD1 RXD0 RX_DV GND VCCD RX_CLK RX_ER TX_ER TX_CLK TX_EN TXD0 TXD1 TXD2 TXD3 GND COL CRS MDINT Type I/O I/O Input - - I/O Input - Output Output Output Output Output - - Output Output Input Output Input Input Input Input Input - Output Output Open Drain Reference for Full Description Table 7 on page 15 Table 7 on page 15 Table 4 on page 14 Table 5 on page 15 Table 5 on page 15 Table 2 on page 13 Table 2 on page 13 Table 4 on page 14 Table 2 on page 13 Table 2 on page 13 Table 2 on page 13 Table 2 on page 13 Table 2 on page 13 Table 5 on page 15 Table 5 on page 15 Table 2 on page 13 Table 2 on page 13 Table 2 on page 13 Table 2 on page 13 Table 2 on page 13 Table 2 on page 13 Table 2 on page 13 Table 2 on page 13 Table 2 on page 13 Table 5 on page 15 Table 2 on page 13 Table 2 on page 13 Table 2 on page 13
12
Datasheet
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet -- LXT972A
2.0
Table 2.
LQFP Pin#
Signal Descriptions
LXT972A MII Signal Descriptions
Type1 Signal Description Data Interface Pins
Symbol
60 59 58 57 56 55 45 46 47 48 49 53 54 52
TXD3 TXD2 TXD1 TXD0 TX_EN TX_CLK RXD3 RXD2 RXD1 RXD0 RX_DV RX_ER TX_ER RX_CLK O O I O Receive Data Valid. The LXT972A asserts this signal when it drives valid data on RXD. This output is synchronous to RX_CLK. Receive Error. Signals a receive error condition has occurred. This output is synchronous to RX_CLK. Transmit Error. Signals a transmit error condition. This signal must be synchronized to TX_CLK. Receive Clock. 25 MHz for 100Mbps operation, 2.5 MHz for 10Mbps operation. Refer to "Clock Requirements" on page 20 in the Functional Description section. Collision Detected. The LXT972A asserts this output when a collision is detected. This output remains High for the duration of the collision. This signal is asynchronous and is inactive during full-duplex operation. Carrier Sense. During half-duplex operation (bit 0.8 = 0), the LXT972A asserts this output when either transmitting or receiving data packets. During full-duplex operation (bit 0.8 = 1), CRS is asserted during receive. CRS assertion is asynchronous with respect to RX_CLK. CRS is de-asserted on loss of carrier, synchronous to RX_CLK. MII Control Interface Pins Management Disable. When MDDIS is High, the MDIO is disabled from read and write operations. When MDDIS is Low at power up or reset, the Hardware Control Interface pins control only the initial or "default" values of their respective register bits. After the power-up/reset cycle is complete, bit control reverts to the MDIO serial channel. Management Data Clock. Clock for the MDIO serial data channel. Maximum frequency is 8 MHz. Management Data Input/Output. Bidirectional serial data channel for PHY/STA communication. Management Data Interrupt. When bit 18.1 = 1, an active Low output on this pin indicates status change. Interrupt is cleared by reading Register 19. O Receive Data. RXD is a bundle of parallel signals that transition synchronously with respect to the RX_CLK. RXD<0> is the least significant bit. I O Transmit Enable. The MAC asserts this signal when it drives valid data on TXD. This signal must be synchronized to TX_CLK. Transmit Clock. TX_CLK is sourced by the PHY in both 10 and 100Mbps operations. 2.5 MHz for 10Mbps operation, 25 MHz for 100Mbps operation. I Transmit Data. TXD is a bundle of parallel data signals that are driven by the MAC. TXD<3:0> shall transition synchronously with respect to the TX_CLK. TXD<0> is the least significant bit.
62
COL
O
63
CRS
O
3
MDDIS
I
43 42 64
MDC MDIO MDINT
I I/O OD
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.
Datasheet
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LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
Table 3.
LQFP Pin# 19 20 23 24
LXT972A Network Interface Signal Descriptions
Type1 Signal Description Twisted-Pair Outputs, Positive & Negative. O During 100BASE-TX or 10BASE-T operation, TPOP/N pins drive 802.3 compliant pulses onto the line. Twisted-Pair Inputs, Positive & Negative. I During 100BASE-TX or 10BASE-T operation, TPIP/N pins receive differential 100BASE-TX or 10BASE-T signals from the line.
Symbol TPOP TPON TPIP TPIN
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain
Table 4.
LQFP Pin#
LXT972A Miscellaneous Signal Descriptions
Symbol Type1 Signal Description Tx Output Slew Controls 0 and 1. These pins select the TX output slew rate (rise and fall time) as follows: TxSLEW1 TxSLEW0 0 1 0 1 Slew Rate (Rise and Fall Time) 2.5 ns 3.1 ns 3.7 ns 4.3 ns
5 6
TxSLEW0 TxSLEW1
I
0 0 1 1
4 12 17 33 34 35 39 1 2 9, 10, 44
RESET ADDR0 RBIAS PAUSE TEST0 TEST1 PWRDWN REFCLK/XI XO N/C
I I AI I I I I I O -
Reset. This active Low input is OR'ed with the control register Reset bit (0.15). The LXT972A reset cycle is extended to 258 s (nominal) after reset is deasserted. Address0. Sets device address. Bias. This pin provides bias current for the internal circuitry. Must be tied to ground through a 22.1 k, 1% resistor. Pause. When set High, the LXT972A advertises Pause capabilities during auto negotiation. Test. Tie Low. Test. Tie Low. Power Down. When set High, this pin puts the LXT972A in a power-down mode. Crystal Input and Output. A 25 MHz crystal oscillator circuit can be connected across XI and XO. A clock can also be used at XI. Refer to Functional Description for detailed clock requirements. No Connection. These pins are not used and should not be terminated.
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain
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Datasheet
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet -- LXT972A
Table 5.
LQFP Pin# 51 7, 11, 13, 14, 15, 16, 18, 25, 26, 32, 41, 50, 61 8, 40 21, 22
LXT972A Power Supply Signal Descriptions
Symbol Type Signal Description Digital Power. Requires a 3.3V power supply.
VCCD
GND
-
Ground.
VCCIO VCCA
-
MII Power. Requires either a 3.3V or a 2.5V supply. Must be supplied from the same source used to power the MAC on the other side of the MII. Analog Power. Requires a 3.3V power supply.
Table 6.
LQFP Pin# 27 28 29 30 31
LXT972A JTAG Test Signal Descriptions
Type1 I O I I
2
Symbol TDI2 TDO2 TMS2 TCK
2
Signal Description Test Data Input. Test data sampled with respect to the rising edge of TCK. Test Data Output. Test data driven with respect to the falling edge of TCK. Test Mode Select. Test Clock. Test clock input sourced by ATE. Test Reset. Test reset input sourced by ATE.
TRST
I
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain. 2. If JTAG port is not used, these pins do not need to be terminated.
Table 7.
LQFP Pin# 38 37 36
LXT972A LED Signal Descriptions
Symbol Type1 Signal Description LED Drivers 1 -3. These pins drive LED indicators. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 50 on page 68 for details). Configuration Inputs 1-3. These pins also provide initial configuration settings (refer to Table 8 on page 24 for details).
LED/CFG1 LED/CFG2 LED/CFG3 I/O
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain
Datasheet
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LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
3.0
3.1
Functional Description
Introduction
The LXT972A is a single-port Fast Ethernet 10/100 Transceiver that supports 10Mbps and 100Mbps networks. It complies with all applicable requirements of IEEE 802.3. The LXT972A can directly drive either a 100BASE-TX line (up to 140 meters) or a 10BASE-T line (up to 185 meters).
3.1.1
Comprehensive Functionality
The LXT972A provides a standard Media Independent Interface (MII) for 10/100 MACs. The LXT972A performs all functions of the Physical Coding Sublayer (PCS) and Physical Media Attachment (PMA) sublayer as defined in the IEEE 802.3 100BASE-X standard. This device also performs all functions of the Physical Media Dependent (PMD) sublayer for 100BASE-TX connections. On power-up, the LXT972A reads its configuration pins to check for forced operation settings. If not configured for forced operation, it uses auto-negotiation/parallel detection to automatically determine line operating conditions. If the PHY device on the other side of the link supports autonegotiation, the LXT972A auto-negotiates with it using Fast Link Pulse (FLP) Bursts. If the PHY partner does not support auto-negotiation, the LXT972A automatically detects the presence of either link pulses (10Mbps PHY) or Idle symbols (100Mbps PHY) and set its operating conditions accordingly. The LXT972A provides half-duplex and full-duplex operation at 100Mbps and 10Mbps.
3.1.2
OSPTM Architecture
Intel's LXT972A incorporates high-efficiency Optimal Signal ProcessingTM design techniques, combining the best properties of digital and analog signal processing to produce a truly optimal device. The receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by as much as 3 dB over an ideal all-analog equalizer. Using OSP mixed-signal processing techniques in the receive equalizer avoids the quantization noise and calculation truncation errors found in traditional DSP-based receivers (typically complex DSP engines with A/D converters). This results in improved receiver noise and cross-talk performance. The OSP signal processing scheme also requires substantially less computational logic than traditional DSP-based designs. This lowers power consumption and also reduces the logic switching noise generated by DSP engines. This logic switching noise can be a considerable source of EMI generated on the device's power supplies. The OSP-based LXT972A provides improved data recovery, EMI performance and low power consumption.
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Datasheet
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet -- LXT972A
3.2
Network Media / Protocol Support
The LXT972A supports both 10BASE-T and 100BASE-TX Ethernet over twisted-pair.
3.2.1
10/100 Network Interface
The network interface port consists of two differential signal pairs. Refer to Table 3 for specific pin assignments. The LXT972A output drivers generate either 100BASE-TX or 10BASE-T. When not transmitting data, the LXT972A generates 802.3-compliant link pulses or idle code. Input signals are decoded either as a 100BASE-TX or 10BASE-T input, depending on the mode selected. Auto-negotiation/ parallel detection or manual control is used to determine the speed of this interface.
3.2.1.1
Twisted-Pair Interface
The LXT972A supports either 100BASE-TX or 10BASE-T connections over 100, Category 5, Unshielded Twisted Pair (UTP) cable. When operating at 100Mbps, the LXT972A continuously transmits and receives MLT3 symbols. When not transmitting data, the LXT972A generates "IDLE" symbols. During 10Mbps operation, Manchester-encoded data is exchanged. When no data is being exchanged, the line is left in an idle state. Link pulses are transmitted periodically to keep the link up. Only a transformer, RJ-45 connector, load resistor, and bypass capacitors are required to complete this interface. On the transmit side, the LXT972A has an active internal termination and does not require external termination resistors. Intel's patented waveshaping technology shapes the outgoing signal to help reduce the need for external EMI filters. Four slew rate settings (refer to Table 4 on page 14) allow the designer to match the output waveform to the magnetic characteristics. On the receive side, the internal impedance is high enough that it has no practical effect on the external termination circuit.
3.2.1.2
Fault Detection and Reporting
The LXT972A supports one fault detection and reporting mechanism. "Remote Fault" refers to a MAC-to-MAC communication function that is essentially transparent to PHY layer devices. It is used only during Auto-Negotiation, and therefore is applicable only to twisted-pair links. "Far-End Fault", on the other hand, is an optional PMA-layer function that may be embedded within PHY devices. The LXT972A supports only the Remote Fault Function, explained in the paragraph that follows.
Remote Fault
Bit 4.13 in the Auto-Negotiation Advertisement Register is reserved for Remote Fault indications. It is typically used when re-starting the auto-negotiation sequence to indicate to the link partner that the link is down because the advertising device detected a fault.
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LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
When the LXT972A receives a Remote Fault indication from its partner during auto-negotiation it:
* sets bit 5.13 in the Link Partner Base Page Ability Register, and * sets the Remote Fault bit 1.4 in the MII Status Register to pass this information to the local
controller.
3.2.2
MII Data Interface
The LXT972A supports a standard Media Independent Interface (MII). The MII consists of a data interface and a management interface. The MII Data Interface passes data between the LXT972A and a Media Access Controller (MAC). Separate parallel buses are provided for transmit and receive. This interface operates at either 10Mbps or 100Mbps. The speed is set automatically, once the operating conditions of the network link have been determined. Refer to "MII Operation" on page 25 for additional details.
3.2.3
Configuration Management Interface
The LXT972A provides both an MDIO interface and a Hardware Control Interface for device configuration and management.
3.2.3.1
MDIO Management Interface
The LXT972A supports the IEEE 802.3 MII Management Interface also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the LXT972A. The MDIO interface consists of a physical connection, a specific protocol that runs across the connection, and an internal set of addressable registers. Some registers are required and their functions are defined by the IEEE 802.3 standard. The LXT972A also supports additional registers for expanded functionality. The LXT972A supports multiple internal registers, each of which is 16 bits wide. Specific register bits are referenced using an "X.Y" notation, where X is the register number (0-31) and Y is the bit number (0-15). The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of this interface is controlled by the MDDIS input pin. When MDDIS is High, the MDIO read and write operations are disabled and the Hardware Control Interface provides primary configuration control. When MDDIS is Low, the MDIO port is enabled for both read and write operations and the Hardware Control Interface is not used.
MDIO Addressing
The protocol allows one controller to communicate between two LXT972A chips. Pin ADDR0 is set high or low to determine the chip address.
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3.3V Dual-Speed Fast Ethernet Transceiver Datasheet -- LXT972A
MDIO Frame Structure
The physical interface consists of a data line (MDIO) and clock line (MDC). The frame structure is shown in Figure 3 and Figure 4 (read and write). MDIO Interface timing is shown in Table 32 on page 53. Figure 3. Management Interface Read Frame Structure
MDC
MDIO (Read)
High Z
32 "1"s Preamble
0 ST
1
1
0 Op Code
A4
A3 PHY Address
A0
R4
R3
R0
Z
0
D15 D15D14 D14 D1 Data Read
D1 D0 Idle
Register Address
Turn Around
Write
Figure 4. Management Interface Write Frame Structure
MDC
MDIO (Write)
Idle
32 "1"s Preamble
0 ST
1
0
1 Op Code
A4
A3 PHY Address
A0
R4
R3
R0
1
0 Turn Around
D15
D14 Data
D1
D0 Idle
Register Address Write
3.2.3.2
MII Interrupts
The LXT972A provides a single interrupt pin (MDINT). Interrupt logic is shown in Figure 5. The LXT972A also provides two dedicated interrupt registers. Register 18 provides interrupt enable and mask functions and Register 19 provides interrupt status. Setting bit 18.1 = 1, enables the device to request interrupt via the MDINT pin. An active Low on this pin indicates a status change on the LXT972A. Interrupts may be caused by four conditions:
* * * *
3.2.3.3
Auto-negotiation complete Speed status change Duplex status change Link status change
Hardware Control Interface
The LXT972A provides a Hardware Control Interface for applications where the MDIO is not desired. The Hardware Control Interface uses the three LED driver pins to set device configuration. Refer to Section 3.4.5, "Hardware Configuration Settings" on page 23 for additional details.
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LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
Figure 5. Interrupt Logic Event X Mask Reg AND Event X Status Reg
Per Event Force Interrupt Interrupt Enable
. . .
OR NAND Interrupt Pin (MDINT)
1. Interrupt (Event) Status Register is cleared on read.
3.3
3.3.1
Operating Requirements
Power Requirements
The LXT972A requires three power supply inputs (VCCD, VCCA, and VCCIO). The digital and analog circuits require 3.3V supplies (VCCD and VCCA). These inputs may be supplied from a single source. Each supply input must be decoupled to ground. An additional supply may be used for the MII (VCCIO). The supply may be either +2.5V or +3.3V. Also, the inputs on the MII interface are tolerant to 5V signals from the controller on the other side of the MII interface. Refer to Table 19 on page 45 for MII I/O characteristics. As a matter of good practice, these supplies should be as clean as possible.
3.3.2
3.3.2.1
Clock Requirements
External Crystal/Oscillator
The LXT972A requires a reference clock input that is used to generate transmit signals and recover receive signals. It may be provided by either of two methods: by connecting a crystal across the oscillator pins (XI and XO), or by connecting an external clock source to pin XI. The connection of a clock source to the XI pin requires the XO pin to be left open. A crystal-based clock is recommended over a derived clock (i.e., PLL-based) to minimize transmit jitter. Refer to the LXT971A/972A Design and Layout Guide for a list of recommended clock sources.
A crystal is typically used in NIC applications. An external 25 MHz clock source, rather than a crystal, is frequently used in switch applications. Refer to Table 20 on page 45 for clock timing requirements
3.3.2.2
MDIO Clock
The MII management channel (MDIO) also requires an external clock. The managed data clock (MDC) speed is a maximum of 8 MHz. Refer to Table 32 on page 53 for details.
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3.3V Dual-Speed Fast Ethernet Transceiver Datasheet -- LXT972A
3.4
Initialization
When the LXT972A is first powered on, reset, or encounters a link failure state, it checks the MDIO register configuration bits to determine the line speed and operating conditions to use for the network link. The configuration bits may be set by the Hardware Control or MDIO interface as shown in Figure 6.
3.4.1
MDIO Control Mode
In the MDIO Control mode, the LXT972A reads the Hardware Control Interface pins to set the initial (default) values of the MDIO registers. Once the initial values are set, bit control reverts to the MDIO interface.
3.4.2
Hardware Control Mode
In the Hardware Control Mode, LXT972A disables direct write operations to the MDIO registers via the MDIO Interface. On power-up or hardware reset the LXT972A reads the Hardware Control Interface pins and sets the MDIO registers accordingly. The following modes are available using either Hardware Control or MDIO Control:
* Force network link operation to:
100TX, Full-Duplex. 100TX, Half-Duplex. 10BASE-T, Full-Duplex. 10BASE-T, Half-Duplex.
* Allow auto-negotiation / parallel-detection.
When the network link is forced to a specific configuration, the LXT972A immediately begins operating the network interface as commanded. When auto-negotiation is enabled, the LXT972A begins the auto-negotiation / parallel-detection operation.
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LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
Figure 6. Initialization Sequence
Power-up or Reset Read H/W Control Interface
Initialize MDIO Registers
MDIO Control Mode
Low
MDDIS Voltage Level?
Hardware Control Mode
High
MDIO Controlled Operation (MDIO Writes Enabled)
Disable MDIO Read and Write Operations
Software Reset?
No
Yes
Reset MDIO Registers to values read at H/W Control Interface at last Hardware Reset
3.4.3
Reduced Power Modes
The LXT972A offers two power-down modes.
3.4.3.1
Hardware Power Down
The hardware power-down mode is controlled by the PWRDWN pin. When PWRDWN is High, the following conditions are true:
* * * *
3.4.3.2
The LXT972A network port and clock are shut down. All outputs are tri-stated. All weak pad pull-up and pull-down resistors are disabled. The MDIO registers are not accessible.
Software Power Down
Software power-down control is provided by bit 0.11 in the Control Register (refer to Table 37 on page 58). During soft power-down, the following conditions are true:
* The network port is shut down. * The MDIO registers remain accessible.
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3.3V Dual-Speed Fast Ethernet Transceiver Datasheet -- LXT972A
3.4.4
Reset
The LXT972A provides both hardware and software resets. Configuration control of AutoNegotiation, speed and duplex mode selection is handled differently for each. During a hardware reset, Auto-Negotiation and Speed are read in from pins (refer to Table 8 on page 24 for pin settings and to Table 37 on page 58 for register bit definitions). During a software reset (0.15 = 1), these bit settings are not re-read from the pins. They revert back to the values that were read in during the last hardware reset. Therefore, any changes to pin values made since the last hardware reset are not detected during a software reset. During a hardware reset, register information is unavailable for 1 ms after de-assertion of the reset. During a software reset (0.15 = 1) the registers are available for reading. The reset bit should be polled to see when the part has completed reset (0.15 = 0).
3.4.5
Hardware Configuration Settings
The LXT972A provides a hardware option to set the initial device configuration. The hardware option uses the three LED driver pins. This provides three control bits, as listed in Table 8. The LED drivers can operate as either open-drain or open-source circuits as shown in Figure 7.
.
Figure 7. Hardware Configuration Settings
3.3V
Configuration Bit = 1 LED/CFG Pin LED/CFG Pin Configuration Bit = 0
1. The LED/CFG pins automatically adjust their polarity upon powerup or reset.
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LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
Table 8.
Hardware Configuration Settings
LED/CFGn Pin Settings1 Resulting Register Bit Values Control Register AutoNeg 0.12 Speed 0.13 0 Full Low Low Low High High High High Low High High Low Low High High High 0 Half 100 Full Half 100 Only Full High Low High 1 1 1 0 1 1 0 1 1 1 1 0 0 1 0 1 1 High Low Low 1 1 0 0 1 0 0 0 1 N/A Auto-Negotiation Advertisement FD 0.8 0 Auto-Neg Advertisement 100FD 4.8 100TX 4.7 10FD 4.6 10T 4.5
Desired Mode
Auto-Neg
Speed (Mbps) 10
Duplex Half
1 Low
2 Low
3 Low
Disabled
Enabled 10/100
Half Only Full or Half
1. Refer to Table 7 on page 15 for LED/CFG pin assignments.
3.5
Establishing Link
See Figure 8 for an overview of link establishment.
3.5.1
Auto-Negotiation
If not configured for forced operation, the LXT972A attempts to auto-negotiate with its link partner by sending Fast Link Pulse (FLP) bursts. Each burst consists of up to 33 link pulses spaced 62.5 s apart. Odd link pulses (clock pulses) are always present. Even link pulses (data pulses) may be present or absent to indicate a "1" or a "0". Each FLP burst exchanges 16 bits of data, which are referred to as a "link code word". All devices that support auto-negotiation must implement the "Base Page" defined by IEEE 802.3 (registers 4 and 5). LXT972A also supports the optional "Next Page" function as described in Table 44 and Table 45 (registers 7 and 8).
3.5.1.1
Base Page Exchange
By exchanging Base Pages, the LXT972A and its link partner communicate their capabilities to each other. Both sides must receive at least three identical base pages for negotiation to continue. Each side identifies the highest common capabilities that both sides support and configures itself accordingly.
3.5.1.2
Next Page Exchange
Additional information, above that required by base page exchange, is also sent via "Next Pages'. The LXT972A fully supports the IEEE 802.3ab method of negotiation via Next Page exchange.
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3.3V Dual-Speed Fast Ethernet Transceiver Datasheet -- LXT972A
3.5.1.3
Controlling Auto-Negotiation
When auto-negotiation is controlled by software, the following steps are recommended:
* After power-up, power-down, or reset, the power-down recovery time, as specified in Table 34
on page 54, must be exhausted before proceeding.
* Set the auto-negotiation advertisement register bits. * Enable auto-negotiation (set MDIO bit 0.12 = 1). 3.5.2 Parallel Detection
For the parallel detection feature of auto-negotiation, the LXT972A also monitors for 10BASE-T Normal Link Pulses (NLP) and 100BASE-TX Idle symbols. If either is detected, the device automatically reverts to the corresponding operating mode. Parallel detection allows the LXT972A to communicate with devices that do not support auto-negotiation. Figure 8. Link Establishment Overview
Power-Up, Reset, or Link Failure
Start Disable Auto-Negotiation 0.12 = 0
Check Value 0.12
0.12 = 1
Enable Auto-Neg/Parallel Detection
Go To Forced Settings
Attempt AutoNegotiation
Listen for 100TX Idle Symbols
Listen for 10T Link Pulses
Done
YES
Link Up?
NO
3.6
MII Operation
The LXT972A device implements the Media Independent Interface (MII) as defined in the IEEE 802.3 standard. Separate channels are provided for transmitting data from the MAC to the LXT972A (TXD), and for passing data received from the line (RXD) to the MAC. Each channel has its own clock, data bus, and control signals. Nine signals are used to pass received data to the MAC: RXD<3:0>, RX_CLK, RX_DV, RX_ER, COL, and CRS. Seven signals are used to transmit data from the MAC: TXD<3:0>, TX_CLK, TX_EN, and TX_ER.
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LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
The LXT972A supplies both clock signals as well as separate outputs for carrier sense and collision. Data transmission across the MII is normally implemented in 4-bit-wide nibbles.
3.6.1
MII Clocks
The LXT972A is the master clock source for data transmission and supplies both MII clocks (RX_CLK and TX_CLK). It automatically sets the clock speeds to match link conditions. When the link is operating at 100Mbps, the clocks are set to 25 MHz. When the link is operating at 10Mbps, the clocks are set to 2.5 MHz. Figure 9 through Figure 11 show the clock cycles for each mode. The transmit data and control signals must always be synchronized to TX_CLK by the MAC. The LXT972A samples these signals on the rising edge of TX_CLK.
3.6.2
Transmit Enable
The MAC must assert TX_EN the same time as the first nibble of preamble, and de-assert TX_EN after the last bit of the packet.
3.6.3
Receive Data Valid
The LXT972A asserts RX_DV when it receives a valid packet. Timing changes depend on line operating speed:
* For 100TX links, RX_DV is asserted from the first nibble of preamble to the last nibble of the
data packet.
* For 10BT links, the entire preamble is truncated. RX_DV is asserted with the first nibble of the
Start of Frame Delimiter (SFD) "5D" and remains asserted until the end of the packet.
3.6.4
Carrier Sense
Carrier sense (CRS) is an asynchronous output. It is always generated when a packet is received from the line and in half-duplex when a packet is transmitted. Carrier sense is not generated when a packet is transmitted and in full-duplex mode. Table 9 summarizes the conditions for assertion of carrier sense, collision, and data loopback signals.
3.6.5
Error Signals
When LXT972A is in 100Mbps mode and receives an invalid symbol from the network, it asserts RX_ER and drives "1110" on the RXD pins. When the MAC asserts TX_ER, the LXT972A drives "H" symbols out on the TPOP/N pins.
3.6.6
Collision
The LXT972A asserts its collision signal, asynchronously to any clock, whenever the line state is half-duplex and the transmitter and receiver are active at the same time. Table 9 summarizes the conditions for assertion of carrier sense, collision, and data loopback signals.
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3.3V Dual-Speed Fast Ethernet Transceiver Datasheet -- LXT972A
Figure 9. 10BASE-T Clocking
2.5 MHz during Auto-Negotiation and 10BASE-T Data & Idle
TX_CLK
(Sourced by LXT972)
2.5 MHz during Auto-Negotiation and 10BASE-T Data & Idle
RX_CLK
(Sourced by LXT972)
Constant 25 MHz
XI
Figure 10. 100BASE-X Clocking
2.5 MHz during Auto-Negotiation 25 MHz once 100BASE-X Link Established
TX_CLK
(Sourced by LXT972)
2.5 MHz during Auto-Negotiation
25 MHz once 100BASE-X Link Established
RX_CLK
(Sourced by LXT972)
Constant 25 MHz
XI
Figure 11. Link Down Clock Transition
Link Down condition/Auto Negotiate Enabled RX_CLK TX_CLK Any Clock 2.5MHz Clock Clock transition time will not exceed 2X the nominal clock period: (10Mbps = 2.5 MHz; 100Mbps = 25 MHz)
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LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
3.6.7
Loopback
The LXT972A provides two loopback functions, operational and test (see Table 9). Loopback paths are shown in Figure 12.
3.6.7.1
Operational Loopback
Operational loopback is provided for 10Mbps half-duplex links when bit 16.8 = 0. Data transmitted by the MAC (TXData) is looped back on the receive side of the MII (RXData). Operational loopback is not provided for 100Mbps links, full-duplex links, or when 16.8 = 1.
3.6.7.2
Test Loopback
A test loopback function is provided for diagnostic testing of the LXT972A. During test loopback, the twisted-pair interface is disabled. Data transmitted by the MAC is internally looped back by the LXT972A and returned to the MAC. Test loopback is available for both 100TX and 10T operation. Test loopback is enabled by setting bits as follows:
* 0.14 = 1 * 0.8 = 1 (full-duplex) * 0.12 = 0 (disable auto-negotiation).
Figure 12. Loopback Paths
LXT972A
MII
10T Loopback
Digital Block
100X Loopback
Analog Block
TX Driver
Table 9.
Speed
Carrier Sense, Loopback, and Collision Conditions
Duplex Condition Full-Duplex Carrier Sense Receive Only Transmit or Receive Receive Only Transmit or Receive Transmit or Receive Test1 Loopback Yes No Yes Yes No Operational Loopback No No No Yes No Collision None Transmit and Receive None Transmit and Receive Transmit and Receive
100Mbps Half-Duplex Full-Duplex 10Mbps Half-Duplex, 16.8 = 0 Half-Duplex, 16.8 = 1
1. Test Loopback is enabled when 0.14 = 1
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3.3V Dual-Speed Fast Ethernet Transceiver Datasheet -- LXT972A
3.7
3.7.1
100Mbps Operation
100BASE-X Network Operations
During 100BASE-X operation, the LXT972A transmits and receives 5-bit symbols across the network link. Figure 13 shows the structure of a standard frame packet. When the MAC is not actively transmitting data, the LXT972A sends out Idle symbols on the line. In 100TX mode, the LXT972A scrambles and transmits the data to the network using MLT-3 line code (Figure 14 on page 29). MLT-3 signals received from the network are descrambled, decoded, and sent across the MII to the MAC.
Figure 13. 100BASE-X Frame Format
64-Bit Preamble (8 Octets) Destination and Source Address (6 Octets each) Packet Length (2 Octets) Data Field Frame Check Field InterFrame Gap / Idle Code (Pad to minimum packet size) (4 Octets) (> 12 Octets)
P0
P1
P6
SFD
DA
DA
SA
SA
L1
L2
D0
D1
Dn
CRC
I0
IFG
Replaced by /J/K/ code-groups Start-of-Stream Delimiter (SSD)
.
Start-of-Frame Delimiter (SFD)
Replaced by /T/R/ code-groups End-of-Stream Delimiter (ESD)
Figure 14. 100BASE-TX Data Path
Standard Data Flow D0 D1 D2 D3
Parallel to Serial
+1 0 0 -1 0
Scramble
D0 D1 D2 D3
Serial to Parallel
4B/5B
S0 S1 S2 S3 S4
DeScramble
MLT3
Transition = 1. No Transition = 0. All transitions must follow pattern: 0, +1, 0, -1, 0, +1...
Scrambler Bypass Data Flow S0 S1 S2 S3 S4
Serial to Parallel Parallel to Serial
+1 0 0 -1 0
S0 S1 S2 S3 S4
MLT3
Transition = 1. No Transition = 0. All transitions must follow pattern: 0, +1, 0, -1, 0, +1...
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LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
As shown in Figure 13 on page 29, the MAC starts each transmission with a preamble pattern. As soon as the LXT972A detects the start of preamble, it transmits a Start-of-Stream Delimiter (SSD, symbols J and K) to the network. It then encodes and transmits the rest of the packet, including the balance of the preamble, the SFD, packet data, and CRC. Once the packet ends, the LXT972A transmits the End-of Stream-Delimiter (ESD, symbols T and R) and then returns to transmitting Idle symbols. 4B/5B coding is shown in Table 10 on page 33. Figure 15 shows normal reception with no errors. When the LXT972A receives invalid symbols from the line, it asserts RX_ER as shown in Figure 16. Figure 15. 100BASE-TX Reception with no Errors
RX_CLK
RX_DV
RXD<3:0>
preamble SFD SFD
DA
DA
DA
DA
CRC
CRC
CRC
CRC
RX_ER
Figure 16. 100BASE-TX Reception with Invalid Symbol
RX_CLK
RX_DV
RXD<3:0>
preamble SFD SFD
DA
DA
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
RX_ER
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3.3V Dual-Speed Fast Ethernet Transceiver Datasheet -- LXT972A
3.7.2
Collision Indication
Figure 17 shows normal transmission. Upon detection of a collision, the COL output is asserted and remains asserted for the duration of the collision as shown in Figure 18.
Figure 17. 100BASE-TX Transmission with no Errors
TX_CLK TX_EN TXD<3:0> CRS COL P R E A M B L E DA DA DA DA DA DA DA DA DA
Figure 18. 100BASE-TX Transmission with Collision
TX_CLK TX_EN TXD<3:0> CRS COL P R E A M B L E JAM JAM JAM JAM
3.7.3
100BASE-X Protocol Sublayer Operations
With respect to the 7-layer communications model, the LXT972A is a Physical Layer 1 (PHY) device. The LXT972A implements the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), and Physical Medium Dependent (PMD) sublayers of the reference model defined by the IEEE 802.3u standard. The following paragraphs discuss LXT972A operation from the reference model point of view.
3.7.3.1
PCS Sublayer
The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B encoding/ decoding function. For 100TX operation, the PCS layer provides IDLE symbols to the PMD-layer line driver as long as TX_EN is de-asserted.
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Preamble Handling
When the MAC asserts TX_EN, the PCS substitutes a /J/K symbol pair, also known as the Start-ofStream Delimiter (SSD), for the first two nibbles received across the MII. The PCS layer continues to encode the remaining MII data, following the coding in Table 10 on page 33, until TX_EN is deasserted. It then returns to supplying IDLE symbols to the line driver. In the receive direction, the PCS layer performs the opposite function, substituting two preamble nibbles for the SSD.
Dribble Bits
The LXT972A handles dribbles bits in all modes. If between one through four dribble bits are received, the nibble is passed across the MII, padded with 1s if necessary. If between five through seven dribble bits are received, the second nibble is not sent onto the MII bus. Figure 19. Protocol Sublayers
MII Interface PCS Sublayer LXT972A
Encoder/Decoder Serializer/De-serializer
PMA Sublayer
Link/Carrier Detect
PMD Sublayer
Scrambler/ De-scrambler
100BASE-TX
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Table 10. 4B/5B Coding
Code Type 4B Code 3210 0000 0001 0010 0011 0100 0101 0110 DATA 0111 1000 1001 1010 1011 1100 1101 1110 1111 IDLE undefined 0101 CONTROL 0101 undefined undefined undefined undefined undefined undefined INVALID undefined undefined undefined undefined undefined undefined undefined 1. 2. 3. 4. Name 0 1 2 3 4 5 6 7 8 9 A B C D E F I
1
5B Code 43210 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 1 1 1 11 11000 10001 01101 00111 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data A Data B Data C Data D Data E Data F
Interpretation
Idle. Used as inter-stream fill code Start-of-Stream Delimiter (SSD), part 1 of 2 Start-of-Stream Delimiter (SSD), part 2 of 2 End-of-Stream Delimiter (ESD), part 1 of 2 End-of-Stream Delimiter (ESD), part 2 of 2 Transmit Error. Used to force signaling errors Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid
J2 K2 T R
3 3
H4 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid
The /I/ (Idle) code group is sent continuously between frames. The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/. The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/. An /H/ (Error) code group is used to signal an error condition.
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LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
3.7.3.2
PMA Sublayer Link
In 100Mbps mode, the LXT972A establishes a link whenever the scrambler becomes locked and remains locked for approximately 50ms. Whenever the scrambler loses lock (receiving less than 12 consecutive idle symbols during a 2ms window), the link are taken down. This provides a very robust link, essentially filtering out any small noise hits that may otherwise disrupt the link. Furthermore, 100M idle patterns will not bring up a 10M link. The LXT972A reports link failure via the MII status bits (1.2 and 17.10) and interrupt functions. If auto-negotiation is enabled, link failure causes the LXT972A to re-negotiate.
Link Failure Override
The LXT972A normally transmits data packets only if it detects the link is up. Setting bit 16.14 = 1 overrides this function, allowing the LXT972A to transmit data packets even when the link is down. This feature is provided as a diagnostic tool. Note that auto-negotiation must be disabled to transmit data packets in the absence of link. If auto-negotiation is enabled, the LXT972A automatically transmits FLP bursts if the link is down.
Carrier Sense
For 100TX links, a start-of-stream delimiter (SSD) or /J/K symbol pair causes assertion of carrier sense (CRS). An end-of-stream delimiter (ESD) or /T/R symbol pair causes de-assertion of CRS. The PMA layer also de-asserts CRS if IDLE symbols are received without /T/R; however, in this case RX_ER is asserted for one clock cycle when CRS is de-asserted. Usage of CRS for Interframe Gap (IFG) timing is not recommended for the following reasons:
* De-assertion time for CRS is slightly longer than assertion time. This causes IFG intervals to
appear somewhat shorter to the MAC than it actually is on the wire.
* CRS de-assertion is not aligned with TX_EN de-assertion on transmit loopbacks in halfduplex mode.
Receive Data Valid
The LXT972A asserts RX_DV to indicate that the received data maps to valid symbols. However, RXD outputs zeros until the received data is decoded and available for transfer to the controller.
3.7.3.3
Twisted-Pair PMD Sublayer
The twisted-pair Physical Medium Dependent (PMD) layer provides the signal scrambling and descrambling, line coding and decoding (MLT-3 for 100TX, Manchester for 10T), as well as receiving, polarity correction, and baseline wander correction functions.
Scrambler/Descrambler
The purpose of the scrambler is to spread the signal power spectrum and further reduce EMI using an 11-bit, data-independent polynomial. The receiver automatically decodes the polynomial whenever IDLE symbols are received.
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Scrambler Seeding. Once the transmit data (or Idle symbols) are properly encoded, they are scrambled to further reduce EMI and to spread the power spectrum using an 11-bit scrambler seed. Five seed bits are determined by the PHY address, and the remaining bits are hard coded in the design. Scrambler Bypass. The scrambler/descrambler can be bypassed by setting bit 16.12 = 1. Scrambler bypass is provided for diagnostic and test support.
Baseline Wander Correction
The LXT972A provides a baseline wander correction function which makes the device robust under all network operating conditions. The MLT3 coding scheme used in 100BASE-TX is by definition "unbalanced". This means that the average value of the signal voltage can "wander" significantly over short time intervals (tenths of seconds). This wander can cause receiver errors at long-line lengths (100 meters) in less robust designs. Exact characteristics of the wander are completely data dependent. The LXT972A baseline wander correction characteristics allow the device to recover error-free data while receiving worst-case "killer" packets over all cable lengths.
Polarity Correction
The 100BASE-TX descrambler automatically detects and corrects for the condition where the receive signal at TPIP and TPIN is inverted.
Programmable Slew Rate Control
The LXT972A device supports a slew rate mechanism whereby one of four pre-selected slew rates can be used. This allows the designer to optimize the output waveform to match the characteristics of the magnetics. The slew rate is determined by the TxSLEW pins as shown in Table 4 on page 14.
3.8
10Mbps Operation
The LXT972A operates as a standard 10BASE-T transceiver. The LXT972A supports all the standard 10Mbps functions. During 10BASE-T (10T) operation, the LXT972A transmits and receives Manchester-encoded data across the network link. When the MAC is not actively transmitting data, the LXT972A drives link pulses onto the line. In 10T mode, the polynomial scrambler/descrambler is inactive. Manchester-encoded signals received from the network are decoded by the LXT972A and sent across the MII to the MAC.
3.8.1
10T Preamble Handling
The LXT972A offers two options for preamble handling, selected by bit 16.5. In 10T Mode when 16.5 = 0, the LXT972A strips the entire preamble off of received packets. CRS is asserted coincident with SFD. RX_DV is held Low for the duration of the preamble. When RX_DV is asserted, the very first two nibbles driven by the LXT972A are the SFD "5D" hex followed by the body of the packet.
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LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
In 10T mode with 16.5 = 1, the LXT972A passes the preamble through the MII and asserts RX_DV and CRS simultaneously. In 10T loopback, the LXT972A loops back whatever the MAC transmits to it, including the preamble.
3.8.2
10T Carrier Sense
For 10T links, CRS assertion is based on reception of valid preamble, and de-assertion on reception of an end-of-frame (EOF) marker. Bit 16.7 allows CRS de-assertion to be synchronized with RX_DV de-assertion. Refer to Table 46 on page 64.
3.8.3
10T Dribble Bits
The LXT972A device handles dribbles bits in all modes. If between one through four dribble bits are received, the nibble is passed across the MII, padded with 1s if necessary. If between five through seven dribble bits are received, the second nibble is not sent onto the MII bus.
3.8.4
10T Link Integrity Test
In 10T mode, the LXT972A always transmits link pulses. When the Link Integrity Test function is enabled (the normal configuration), it monitors the connection for link pulses. Once link pulses are detected, data transmission is enabled and remains enabled as long as either the link pulses or data transmission continue. If the link pulses stop, the data transmission is disabled. If the Link Integrity Test function is disabled, the LXT972A transmits to the connection regardless of detected link pulses. The Link Integrity Test function can be disabled by setting bit 16.14 = 1.
3.8.4.1
Link Failure
Link failure occurs if Link Integrity Test is enabled and link pulses or packets stop being received. If this condition occurs, the LXT972A returns to the auto-negotiation phase if auto-negotiation is enabled. If the Link Integrity Test function is disabled by setting 16.14 = 1 in the Configuration Register, the LXT972A transmits packets, regardless of link status.
3.8.5
10T SQE (Heartbeat)
By default, the Signal Quality Error (SQE) or heartbeat function is disabled on the LXT972A. To enable this function, set bit 16.9 = 1. When this function is enabled, the LXT972A asserts its COL output for 5-15 BT after each packet. See Figure 29 on page 51 for SQE timing parameters.
3.8.6
10T Jabber
If a transmission exceeds the jabber timer, the LXT972A disables the transmit and loopback functions. See Figure 28 on page 51 for jabber timing parameters. The LXT972A automatically exits jabber mode after the unjabber time has expired. This function can be disabled by setting bit 16.10 = 1.
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3.8.7
10T Polarity Correction
The LXT972A automatically detects and corrects for the condition where the receive signal (TPIP/ N) is inverted. Reversed polarity is detected if eight inverted link pulses, or four inverted end-offrame (EOF) markers, are received consecutively. If link pulses or data are not received by the maximum receive time-out period (96-128 ms), the polarity state is reset to a non-inverted state.
3.9
3.9.1
Monitoring Operations
Monitoring Auto-Negotiation
Auto-negotiation can be monitored as follows:
* Bit 17.7 is set to 1 once the Auto-Negotiation process is completed. * Bits 1.2 and 17.10 are set to 1 once the link is established. * Bits 17.14 and 17.9 can be used to determine the link operating conditions (speed and duplex).
3.9.1.1 Monitoring Next Page Exchange
The LXT972A offers an Alternate Next Page mode to simplify the next page exchange process. Normally, bit 6.1 (Page Received) remains set until read. When Alternate Next Page mode is enabled (16.1 = 1), bit 6.1 is automatically cleared whenever a new negotiation process takes place. This prevents the user from reading an old value in 6.1 and assuming that Registers 5 and 8 (Partner Ability) contain valid information. Additionally, the LXT972A uses bit 6.5 to indicate when the current received page is the base page. This information is useful for recognizing when next pages must be resent due to a new negotiation process starting. Bits 6.1 and 6.5 are cleared when read.
3.9.2
LED Functions
The LXT972A incorporates three direct LED drivers. On power up all the drivers are asserted for approximately 1 second after reset de-asserts. Each LED driver can be programmed using the LED Configuration Register (refer to Table 50 on page 68) to indicate one the following conditions:
* * * * * *
Operating Speed Transmit Activity Receive Activity Collision Condition Link Status Duplex Mode
The LED drivers can also be programmed to display various combined status conditions. For example, setting bits 20.15:12 = 1101 produces the following combination of Link and Activity indications:
* If Link is down LED is off. * If Link is up LED is on.
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LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
* If Link is up and activity is detected, the LED blinks at the stretch interval selected by bits
20.3:2 and continues to blink as long as activity is present. The LED driver pins also provide initial configuration settings. The LED pins are sensitive to polarity and automatically pulls up or pulls down to configure for either open drain or open source circuits (10 mA Max current rating) as required by the hardware configuration. Refer to the discussion of "Hardware Configuration Settings" on page 23 for details.
3.9.2.1
LED Pulse Stretching
The LED Configuration Register also provides optional LED pulse stretching to 30, 60, or 100 ms. If during this pulse stretch period the event occurs again, the pulse stretch time is further extended. When an event such as receiving a packet occurs, it is edge detected and starts the stretch timer. The LED driver remains asserted until the stretch timer expires. If another event occurs before the stretch timer expires, the stretch timer is reset and the stretch time is extended. When a long event (such as duplex status) occurs, it is edge detected and starts the stretch timer. When the stretch timer expires the edge detector is reset so that a long event causes another pulse to be generated from the edge detector, which resets the stretch timer and causes the LED driver to remain asserted. Figure 20 shows how the stretch operation functions.
Figure 20. LED Pulse Stretching Event
LED
stretch stretch stretch Note: The direct drive LED outputs in this diagram are shown as active Low.
3.10
Boundary Scan (JTAG1149.1) Functions
LXT972A includes a IEEE 1149.1 boundary scan test port for board level testing. All digital input, output, and input/output pins are accessible. The BSDL file is available by contacting your local sales office (see the back page) or by accessing the Intel web site (developer.intel.com/design/ network/).
3.10.1
Boundary Scan Interface
This interface consists of five pins (TMS, TDI, TDO, TRST, and TCK). It includes a state machine, data register array, and instruction register. The TMS and TDI pins are internally pulled up. TCK is internally pulled down. TDO does not have an internal pull-up or pull-down.
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3.3V Dual-Speed Fast Ethernet Transceiver Datasheet -- LXT972A
3.10.2
State Machine
The TAP controller is a 16 state machine driven by the TCK and TMS pins. Upon reset the TEST_LOGIC_RESET state is entered. The state machine is also reset when TMS and TDI are high for five TCK periods.
3.10.3
Instruction Register
After the state machine resets, the IDCODE instruction is always invoked. The decode logic ensures the correct data flow to the Data registers according to the current instruction. Valid instructions are listed in Table 12.
3.10.4
Boundary Scan Register (BSR)
Each Boundary Scan Register (BSR) cell has two stages. A flip-flop and a latch are used for the serial shift stage and the parallel output stage. There are four modes of operation as listed in Table 11.
Table 11. BSR Mode of Operation
Mode 1 2 3 4 Description Capture Shift Update System Function
Table 12. Supported JTAG Instructions
Name EXTEST IDCODE SAMPLE TRIBYP SETBYP BYPASS Code 0000 0001 0010 0011 0100 1111 Description External Test ID Code Inspection Sample Boundary Force Float Control Boundary to 1/0 Bypass Scan Mode Test Normal Normal Normal Test Normal Data Register BSR ID REG BSR Bypass Bypass Bypass
Table 13. Device ID Register
31:28 Version 0001 27:12 Part ID (hex) 03CB 11:8 Jedec Continuation Characters 1110 7:1 JEDEC ID1 111 1110 0 Reserved 1
1. The JEDEC IS is an 8-bit identifier. The MSB is for parity and is ignored. Intel's JEDEC ID is FE (1111 1110) which becomes 111 1110
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LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
4.0
4.1
Application Information
Magnetics Information
The LXT972A requires a 1:1 ratio for both the receive and transmit transformers. The transformer isolation voltage should be rated at 2kV to protect the circuitry from static voltages across the connectors and cables. Refer to Table 14 for transformer requirements. A cross-reference list of magnetic manufacturers and part numbers is available in Application Note 073, Magnetic Manufacturers, which can be found on the Intel web site (developer.intel.com/ design/network/). Before committing to a specific component, designers should contact the manufacturer for current product specifications, and validate the magnetics for the specific application.
Table 14. Magnetics Requirements
Parameter Rx turns ratio Tx turns ratio Insertion loss Primary inductance Transformer isolation Differential to common mode rejection Min - - 0.0 350 - 40 35 -16 Return Loss -10 - - dB 80 MHz Nom 1:1 1:1 0.6 - 1.5 - - - Max - - 1.1 - - - - - Units - - dB Test Condition
H
kV dB dB dB .1 to 60 MHz 60 to 100 MHz 30 MHz
4.2
Typical Twisted-Pair Interface
Table 15 provides a comparison of the RJ-45 connections for NIC and switch applications in a typical twisted-pair interface setting.
Table 15. RJ-45 Pin Comparison of NIC and Switch Twisted-Pair Interfaces
RJ-45 Symbol Switch TPIP TPIN TPOP TPON 1 2 3 6 NIC 3 6 1 2
Figure 21 on page 41 shows a typical twisted-pair interface with the RJ-45 connections crossed over for a switch configuration. Figure 22 on page 42 provides a typical twisted-pair interface with the RJ-45 connections configured for a NIC application.
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Figure 21. Typical Twisted-Pair Interface - Switch
270 pF 5%
TPIP
50 1% 0.01 F 50 1% 1:1
RJ-45
1
3
50 50
2 3 4
TPIN TPOP
270 pF 5% 1:1
50
5 6
LXT972A
TPON
2
0.1F 50
50
7
50
8
1
*
*
* = 0.001 F / 2.0 kV
4
VCCA
0.1F .01F
GND
1. Center tap current may be supplied from 3.3V VCCA as shown. Additional power savings may be realized by supplying the center tap from a 2.5V current source. A separate ferrite bead (rated at 50 mA) should be used to supply center tap current. 2. The 100 transmit load termination resistor typically required is integrated in the LXT972A. 3. Magnetics without a receive pair center tap do not require a 2 kV termination. 4. RJ-45 connections shown are for a standard switch application. For a standard NIC RJ-45 setup, see Figure 22.
Datasheet
To Twisted-Pair Network
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LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
Figure 22. Typical Twisted-Pair Interface - NIC
RJ-45 270 pF 5% 50 50
8 7
50 1% 0.01 F 50 1%
1:1
6
3
50 50 50
5 4 3
TPIP TPON
270 pF 5% 1:1
2 1
LXT972A
TPOP
2
0.1F
4 1
* = 0.001 F / 2.0 kV
*
*
VCCA
0.1F .01F
GND
1. Center tap current may be supplied from 3.3V VCCA as shown. Additional power savings may be realized by supplying the center tap from a 2.5V current source. A separate ferrite bead (rated at 50 mA) should be used to supply center tap current. 2. The 100 transmit load termination resistor typically required is integrated in the LXT972A. 3. Magnetics without a receive pair center tap do not require a 2kV termination. 4. RJ-45 connections shown are for a standard NIC. Tx/Rx crossover may be required for repeater & switch applications.
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To Twisted-Pair Network
TPIN
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3.3V Dual-Speed Fast Ethernet Transceiver Datasheet -- LXT972A
Figure 23. Typical MII Interface
TX_EN TX_ER TXD<3:0> TX_CLK RX_CLK
MAC
RX_DV RX_ER RXD<3:0> CRS COL
LXT972A
X F M R
RJ-45
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LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
5.0
Note:
Test Specifications
Table 16 through Table 34 and Figure 24 through Figure 35 represent the target specifications of the LXT972A. These specifications are guaranteed by test except where noted "by design." Minimum and maximum values listed in Table 18 through Table 34 apply over the recommended operating conditions specified in Table 17.
5.1
Electrical Parameters
Table 16. Absolute Maximum Ratings
Parameter Supply voltage Operating temperature Storage temperature Sym VCC TOPA TST Min -0.3 0 -65 Max 4.0 +70 +150 Units V C C
Caution: Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 17. Operating Conditions
Parameter Recommended operating temperature Recommended supply voltage2 LXT972A_C (Commercial) Analog & Digital I/O 100BASE-TX 10BASE-T VCC current Power Down Auto-Negotiation ICC ICC - - - - 1 110 mA mA Sym TOPA Vcca, Vccd Vccio ICC ICC Min 0 3.14 2.35 - - Typ1 - 3.3 - - - Max 70 3.45 3.45 110 82 Units C V V mA mA
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Voltages with respect to ground unless otherwise specified.
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Table 18. Digital I/O Characteristics 1
Parameter Input Low voltage Input High voltage Input current Output Low voltage Output High voltage Symbol VIL VIH II VOL VOH Min - 2.0 -10 - 2.4 Typ2 - - - - - Max 0.8 - 10 0.4 - Units V V Test Conditions - - 0.0 < VI < VCC IOL = 4 mA IOH = -4 mA
A
V V
1. Applies to all pins except MII, LED and XI/XO pins. Refer to Table 19 for MII I/O Characteristics, Table 20 for XI/XO and Table 21 for LED Characteristics. 2. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
Table 19. Digital I/O Characteristics - MII Pins
Parameter Input Low voltage Input High voltage Input current Output Low voltage Output High voltage VOH Driver output resistance (Line driver output enabled) RO RO
2 2
Symbol VIL VIH II VOL VOH
Min - 2.0 -10 - 2.2 2.0 - -
Typ1 - - - - - - 100 100
Max 0.8 - 10 0.4 - - - -
Units V V
Test Conditions - - 0.0 < VI < VCCIO IOL = 4 mA IOH = -4 mA, VCCIO = 3.3V IOH = -4 mA, VCCIO = 2.5V VCCIO = 2.5V VCCIO = 3.3V
A
V V V

1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Parameter is guaranteed by design; not subject to production testing.
Table 20. I/O Characteristics - REFCLK/XI and XO Pins
Parameter Input Low Voltage Input High Voltage Input Clock Frequency Tolerance2 Input Clock Duty Cycle2 Input Capacitance Sym VIL VIH Min - 2.0 - 35 - Typ1 - - - - 3.0 Max 0.8 - Units V V ppm % pF Test Conditions
f
Tdc CIN
100
65 -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Parameter is guaranteed by design; not subject to production testing.
Table 21. I/O Characteristics - LED/CFG Pins
Parameter Output Low Voltage Output High Voltage Input Current Sym Vol Voh II Min - 2.4 -10 Typ - - - Max 0.4 - 10 Units V V Test Conditions IOL = 10 mA IOH = -10 mA 0 < VI < VCCIO
A
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LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
Table 22. 100BASE-TX Transceiver Characteristics
Parameter Peak differential output voltage Signal amplitude symmetry Signal rise/fall time Rise/fall time symmetry Duty cycle distortion Overshoot/Undershoot Jitter (measured differentially) Sym VP Vss TRF TRFS DCD VOS - Min 0.95 98 3.0 - 35 - - Typ1 - - - - 50 - - Max 1.05 102 5.0 0.5 65 5 1.4 Units V % ns ns % % ns Test Conditions Note 2 Note 2 Note 2 Note 2 Offset from 16ns pulse width at 50% of pulse peak - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Measured at the line side of the transformer, line replaced by 100(+/-1%) resistor.
Table 23. 10BASE-T Transceiver Characteristics
Parameter Sym Min Transmitter Peak differential output voltage VOP 2.2 2.5 2.8 V With transformer, line replaced by 100 resistor After line model specified by IEEE 802.3 for 10BASE-T MAU Typ Max Units Test Conditions
Transition timing jitter added by the MAU and PLS sections
-
0 Receiver
2
11
ns
Receive Input Impedance Differential Squelch Threshold
ZIN VDS
300
420
22 585
k mV
Table 24. 10BASE-T Link Integrity Timing Characteristics
Parameter Time Link Loss Receive Link Pulse Link Min Receive Timer Link Max Receive Timer Link Transmit Period Link Pulse Width Sym TLL TLP TLR MIN TLR MAX Tlt Tlpw Min 50 2 2 50 8 60 Typ - - - - - - Max 150 7 7 150 24 150 Units ms Link Pulses ms ms ms ns Test Conditions - - - - - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
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5.2
Timing Diagrams
Figure 24. 100BASE-TX Receive Timing - 4B Mode
0ns 250ns
TPI t4 CRS t3 RX_DV t1 t2 RXD<3:0> RX_CLK t6 COL t7 t5
Table 25. 100BASE-TX Receive Timing Parameters - 4B Mode
Parameter RXD<3:0>, RX_DV, RX_ER setup to RX_CLK High RXD<3:0>, RX_DV, RX_ER hold from RX_CLK High CRS asserted to RXD<3:0>, RX_DV Receive start of "J" to CRS asserted Receive start of "T" to CRS de-asserted Receive start of "J" to COL asserted Receive start of "T" to COL de-asserted Sym t1 t2 t3 t4 t5 t6 t7 Min 10 10 3 12 10 16 17 Typ1 - - - - - - - Max - - 5 16 17 22 20 Units2 ns ns BT BT BT BT BT Test Conditions - - - - - - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 100BASE-T bit time = 108 s or 10 ns.
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LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
Figure 25. 100BASE-TX Transmit Timing - 4B Mode
0ns 250ns
t1 TXCLK TX_EN t2 TXD<3:0> t5 TPO t3 CRS
Table 26. 100BASE-TX Transmit Timing Parameters - 4B Mode
Parameter TXD<3:0>, TX_EN, TX_ER setup to TX_CLK High TXD<3:0>, TX_EN, TX_ER hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted TX_EN sampled to TPO out (Tx latency) Sym t1 t2 t3 t4 t5 Min 12 0 20 24 5.3 Typ1 - - - - - Max - - 24 28 5.7 Units2 ns ns BT BT BT Test Conditions - - - - -
t4
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 100BASE-T bit time = 108 s or 10 ns.
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Figure 26. 10BASE-T Receive Timing
RX_CLK t3 RXD, RX_DV, RX_ER t1 t2
t4
t5
CRS t6 TPI t9 COL t8 t7
Table 27. 10BASE-T Receive Timing Parameters
Parameter RXD, RX_DV, RX_ER Setup to RX_CLK High RXD, RX_DV, RX_ER Hold from RX_CLK High TPIP/N in to RXD out (Rx latency) CRS asserted to RXD, RX_DV, RX_ER asserted RXD, RX_DV, RX_ER de-asserted to CRS deasserted TPI in to CRS asserted TPI quiet to CRS de-asserted TPI in to COL asserted TPI quiet to COL de-asserted Sym t1 t2 t3 t4 t5 t6 t7 t8 t9 Min 10 10 5.8 5 0.3 2 6 1 5 Typ1 - - - - - - - - - Max - - 6.0 32 0.5 28 10 31 10 Units2 ns ns BT BT BT BT BT BT BT Test Conditions - - - - - - - - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 10BASE-T bit time = 107 s or 100 ns.
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LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
Figure 27. 10BASE-T Transmit Timing
TX_CLK t1 TXD, TX_EN, TX_ER t2
t3
t4
CRS t5 TPO
Table 28. 10BASE-T Transmit Timing Parameters
Parameter TXD, TX_EN, TX_ER setup to TX_CLK High TXD, TX_EN, TX_ER hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted TX_EN sampled to TPO out (Tx latency) Sym t1 t2 t3 t4 t5 Min 10 0 - - - Typ1 - - 2 1 72.5 Max - - - - - Units2 ns ns BT BT BT Test Conditions - - - - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 10BASE-T bit time = 107 s or 100 ns.
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Figure 28. 10BASE-T Jabber and Unjabber Timing
TX_EN t1 TXD
t2 COL
Table 29. 10BASE-T Jabber and Unjabber Timing Parameters
Parameter Maximum transmit time Unjab time Sym t1 t2 Min 20 250 Typ1 - - Max 150 750 Units ms ms Test Conditions - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
Figure 29. 10BASE-T SQE (Heartbeat) Timing
TX_CLK
TX_EN t1 COL t2
Table 30. 10BASE-T SQE Timing Parameters
Parameter COL (SQE) Delay after TX_EN off COL (SQE) Pulse duration Sym t1 t2 Min 0.65 0.5 Typ1 - - Max 1.6 1.5 Units us us Test Conditions - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
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LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
Figure 30. Auto Negotiation and Fast Link Pulse Timing
Clock Pulse
Data Pulse
Clock Pulse
TPO
t1 t2 t3 t1
Figure 31. Fast Link Pulse Timing
FLP Burst
FLP Burst
TPO
t4 t5
Table 31. Auto Negotiation and Fast Link Pulse Timing Parameters
Parameter Clock/Data pulse width Clock pulse to Data pulse Clock pulse to Clock pulse FLP burst width FLP burst to FLP burst Clock/Data pulses per burst Sym t1 t2 t3 t4 t5 - Min - 55.5 123 - 8 17 Typ1 100 - - 2 12 - Max - 63.8 127 - 24 33 Units ns Test Conditions - - - - - -
s s
ms ms ea
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
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Figure 32. MDIO Input Timing
MDC
t1 t2
MDIO
Figure 33. MDIO Output Timing
t4 MDC t3
MDIO
Table 32. MDIO Timing Parameters
Parameter MDIO setup before MDC, sourced by STA MDIO hold after MDC, sourced by STA MDC to MDIO output delay, source by PHY MDC period Sym t1 t2 t3 t4 Min 10 5 - 125 Typ1 - - - - Max - - 150 - Units ns ns ns ns Test Conditions - - - MDC = 8 MHz
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
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LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
Figure 34. Power-Up Timing
v1 VCC MDIO,etc t1
Table 33. Power-Up Timing Parameters
Parameter Voltage threshold Power Up delay
2
Sym v1 t1
Min - -
Typ1 2.9 -
Max - 300
Units V
Test Conditions - -
s
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Power Up Delay is specified as a maximum value because it refers to the PHY's guaranteed performance - the PHY comes out of reset after a delay of No MORE Than 300 s. System designers should consider this as a minimum value - After threshold v1 is reached, the MAC should delay No LESS Than 300 s before accessing the MDIO port.
Figure 35. RESET Pulse Width and Recovery Timing
RESET
t1 t2
MDIO,etc
Table 34. RESET Pulse Width and Recovery Timing Parameters
Parameter RESET pulse width RESET recovery delay
2
Sym t1 t2
Min 10 -
Typ1 - -
Max - 300
Units ns
Test Conditions - -
s
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Reset Recovery Delay is specified as a maximum value because it refers to the PHY's guaranteed performance - the PHY comes out of reset after a delay of No MORE Than 300 s. System designers should consider this as a minimum value After de-asserting RESET*, the MAC should delay No LESS Than 300 s before accessing the MDIO port.
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6.0
Register Definitions
The LXT972A register set includes multiple 16-bit registers. Refer to Table 35 for a complete register listing.
* Base registers (0 through 8) are defined in accordance with the "Reconciliation Sublayer and
Media Independent Interface" and "Physical Layer Link Signaling for 10/100Mbps AutoNegotiation" sections of the IEEE 802.3 standard.
* Additional registers are defined in accordance with the IEEE 802.3 standard for adding unique
chip functions. Table 35. Register Set
Address 0 1 2 3 4 5 6 7 8 9 10 15 16 17 18 19 20 21- 29 30 Control Register Status Register #1 PHY Identification Register 1 PHY Identification Register 2 Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Base Page Ability Register Auto-Negotiation Expansion Register Auto-Negotiation Next Page Transmit Register Auto-Negotiation Link Partner Received Next Page Register 1000BASE-T/100BASE-T2 Control Register 1000BASE-T/100BASE-T2 Status Register Extended Status Register Port Configuration Register Status Register #2 Interrupt Enable Register Interrupt Status Register LED Configuration Register Reserved Transmit Control Register Refer to Table 51 on page 69 Register Name Bit Assignments Refer to Table 37 on page 58 Refer to Table 38 on page 58 Refer to Table 39 on page 59 Refer to Table 40 on page 60 Refer to Table 41 on page 61 Refer to Table 42 on page 62 Refer to Table 43 on page 63 Refer to Table 44 on page 63 Refer to Table 45 on page 64 Not Implemented Not Implemented Not Implemented Refer to Table 46 on page 64 Refer to Table 47 on page 65 Refer to Table 48 on page 66 Refer to Table 49 on page 66 Refer to Table 50 on page 68
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55
Table 36. Register Bit Map
Bit Fields Reg Title B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Addr
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LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
Control Register Control Reset Loopback Speed Select A/N Enable Power Down Isolate Re-start A/N Duplex Mode COL Test Speed Select Reserved 0
Status Register Status 100BaseT4 100Base- 100Base- 10Mbps X Full X Half Full Duplex Duplex Duplex MF 10Mbps 100Base- 100BaseA/N Remote A/N Ability Half T2 Full T2 Half Extended Reserved Preamble Complete Fault Status Suppress Duplex Duplex Duplex PHY ID Registers PHY ID 1 PHY ID2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2 3 Link Status Jabber Detect Extended Capability 1
PHY ID No
MFR Model No Auto-Negotiation Advertisement Register
MFR Rev No
A/N Advertise
Next Page
Reserved
Remote Reserved Fault
Asymm Pause
Pause
100BaseT4
10Base-T 100Base100BaseFull 10Base-T TX Full TX Duplex Duplex
IEEE Selector Field
4
Auto-Negotiation Link Partner Base Page Ability Register A/N Link Ability Next Page Ack Remote Reserved Fault Asymm Pause Pause 100Base- 100Base- 100Base- 10Base-T Full 10Base-T TX Full TX T4 Duplex Duplex IEEE Selector Field 5
Auto-Negotiation Expansion Register A/N Expansion Base Page Parallel Detect Fault Link Link Partner Next Page Partner Next Page Able Received A/N Able Page Able
Reserved
6
Auto-Negotiation Next Page Transmit Register A/N Next Page Txmit Next Page Reserved Message Page Ack 2 Toggle Message / Unformatted Code Field 7
Auto-Negotiation Link Partner Next Page Receive Register A/N Link Next Page Next Page Ack Message Page Ack 2 Toggle Configuration Register Port Config Reserved Force Link Pass Bypass Txmit Scrambler Reserved Disable ) (100TX) Jabber (10T) SQE (10T) TP Loopback (10T) CRS Select (10T) Reserved PRE_EN Reserved Reserved Alternate Next Reserved Page 16 Message / Unformatted Code Field 8
Table 36. Register Bit Map (Continued)
Bit Fields Reg Title B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Addr
Datasheet 57
Status Register #2 Status Register #2 Reserved 10/100 Mode Transmit Status Receive Status Collision Status Link Duplex Mode Auto-Neg Auto-Neg Reserved Complete Polarity Pause Error Reserved Reserved 17
Interrupt Enable Register Interrupt Enable Reserved Reserved Auto-Neg Mask Speed Mask Duplex Mask Link Mask Reserved Reserved Interrupt Enable Test Interrupt 18
Interrupt Status Register Interrupt Status Reserved Reserved Auto-Neg Done Speed Change Duplex Change MD Link Reserved Reserved Reserved Interrupt Change 19
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet -- LXT972A
LED Configuration Register LED Config LED1 LED2 Transmit Control Register Trans. Control Reserved Transmit Low Pwr Port Rise Time Control Reserved 30 LED3 LED Freq Pulse Stretch Reserved 20
LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
Table 37. Control Register (Address 0)
Bit 0.15 0.14 Reset Loopback Name 1 = PHY reset 0 = Normal operation 1 = Enable loopback mode 0 = Disable loopback mode 0.6 0.13 Speed Selection 1 1 0 0 1 0 1 0 0.13 Speed Selected Reserved 1000Mbps (not supported) 100Mbps 10Mbps R/W Note 2 Description Type 1 R/W SC R/W Default 0 0
0.12 0.11 0.10 0.9 0.8 0.7
Auto-Negotiation Enable Power-Down Isolate Restart Auto-Negotiation Duplex Mode Collision Test
1 = Enable Auto-Negotiation Process 0 = Disable Auto-Negotiation Process 1 = Power-down 0 = Normal operation 1 = Electrically isolate PHY from MII 0 = Normal operation 1 = Restart Auto-Negotiation Process 0 = Normal operation 1 = Full Duplex 0 = Half Duplex 1 = Enable COL signal test 0 = Disable COL signal test 0.6 0.13 1 0 1 0 Speed Selected Reserved 1000Mbps (not supported) 100Mbps 10Mbps
R/W R/W R/W R/W SC R/W R/W
Note 2 0 0 0 Note 2 0
0.6
Speed Selection
1 1 0 0
R/W
0
0.5:0
Reserved
Write as 0, ignore on Read
R/W
00000
1. R/W = Read/Write RO = Read Only SC = Self Clearing 2. Default value of bits 0.12, 0.13 and 0.8 are determined by the LED/CFG pins (refer to Table 8 on page 24).
Table 38. MII Status Register #1 (Address 1)
Bit 1.15 1.14 1.13 Name 100BASE-T4 Not Supported 100BASE-X FullDuplex 100BASE-X HalfDuplex Description 1 = PHY able to perform 100BASE-T4 0 = PHY not able to perform 100BASE-T4 1 = PHY able to perform full-duplex 100BASE-X 0 = PHY not able to perform full-duplex 100BASE-X 1 = PHY able to perform half-duplex 100BASE-X 0 = PHY not able to perform half-duplex 100BASE-X Type 1 RO RO RO Default 0 1 1
1. RO = Read Only LL = Latching Low LH = Latching High
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Datasheet
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet -- LXT972A
Table 38. MII Status Register #1 (Address 1)
Bit 1.12 1.11 Name 10Mbps Full-Duplex 10Mbps Half-Duplex 100BASE-T2 FullDuplex Not Supported 1.9 100BASE-T2 HalfDuplex Not Supported 1.8 1.7 1.6 Extended Status Reserved MF Preamble Suppression Auto-Negotiation Complete Remote Fault Auto-Negotiation Ability Link Status Jabber Detect Extended Capability Description 1 = PHY able to operate at 10Mbps in full-duplex mode 0 = PHY not able to operate at 10Mbps full-duplex mode 1 = PHY able to operate at 10Mbps in half-duplex mode 0 = PHY not able to operate at 10Mbps in half-duplex 1 = PHY able to perform full-duplex 100BASE-T2 0 = PHY not able to perform full-duplex 100BASE-T2 1 = PHY able to perform half duplex 100BASE-T2 0 = PHY not able to perform half-duplex 100BASE-T2 1 = Extended status information in register 15 0 = No extended status information in register 15 1 = ignore when read 1 = PHY accepts management frames with preamble suppressed 0 = PHY will not accept management frames with preamble suppressed 1 = Auto-negotiation complete 0 = Auto-negotiation not complete 1 = Remote fault condition detected 0 = No remote fault condition detected 1 = PHY is able to perform Auto-Negotiation 0 = PHY is not able to perform Auto-Negotiation 1 = Link is up 0 = Link is down 1 = Jabber condition detected 0 = Jabber condition not detected 1 = Extended register capabilities 0 = Basic register capabilities Type 1 RO RO Default 1 1
1.10
RO
0
RO
0
RO RO RO
0 0 0
1.5 1.4 1.3 1.2 1.1 1.0
RO RO/LH RO RO/LL RO/LH RO
0 0 1 0 0 1
1. RO = Read Only LL = Latching Low LH = Latching High
Table 39. PHY Identification Register 1 (Address 2)
Bit 2.15:0 Name PHY ID Number Description The PHY identifier composed of bits 3 through 18 of the OUI. Type 1 RO Default 0013 hex
1. RO = Read Only
Datasheet
59
LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
Table 40. PHY Identification Register 2 (Address 3)
Bit 3.15:10 3.9:4 Name PHY ID number Manufacturer's model number Manufacturer's revision number Description The PHY identifier composed of bits 19 through 24 of the OUI. 6 bits containing manufacturer's part number. Type 1 RO RO Default 011110 001110 xxxx 4 bits containing manufacturer's revision number. RO (See LXT971A/972A Specification Update)
3.3:0
1. RO = Read Only
Figure 36. PHY Identifier Bit Mapping
a bc Organizationally Unique Identifier rs x
PHY ID Register #1 (address 2) = 0013 15 0 15
PHY ID Register #2 (Address 3) 10 9 4 3 0
0000000000000100110111100011100000
00
20
7B
5
0
3
0
The Intel OUI is 00207B hex Manufacturer's Model Number Revision Number
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Datasheet
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet -- LXT972A
Table 41. Auto Negotiation Advertisement Register (Address 4)
Bit 4.15 4.14 4.13 4.12 4.11 4.10 Name Next Page Reserved Remote Fault Reserved Asymmetric Pause Pause Description 1 = Port has ability to send multiple pages. 0 = Port has no ability to send multiple pages. Ignore. 1 = Remote fault. 0 = No remote fault. Ignore. Pause operation defined in Clause 40 and 27. 1 = Pause operation enabled for full-duplex links. 0 = Pause operation disabled. 1 = 100BASE-T4 capability is available. 0 = 100BASE-T4 capability is not available. 4.9 100BASE-T4 (The LXT972A does not support 100BASE-T4 but allows this bit to be set to advertise in the Auto-Negotiation sequence for 100BASE-T4 operation. An external 100BASE-T4 transceiver could be switched in if this capability is desired.) 1 = Port is 100BASE-TX full-duplex capable. 0 = Port is not 100BASE-TX full-duplex capable. 1 = Port is 100BASE-TX capable. 0 = Port is not 100BASE-TX capable. 1 = Port is 10BASE-T full-duplex capable. 0 = Port is not 10BASE-T full-duplex capable. 1 = Port is 10BASE-T capable. 0 = Port is not 10BASE-T capable. <00001> = IEEE 802.3. <00010> = IEEE 802.9 ISLAN-16T. <00000> = Reserved for future Auto-Negotiation development. <11111> = Reserved for future Auto-Negotiation development. Unspecified or reserved combinations should not be transmitted. R/W 0 Type 1 R/W RO R/W R/W R/W R/W Default 0 0 0 0 0 Note 2
4.8 4.7 4.6 4.5
100BASE-TX full-duplex 100BASE-TX 10BASE-T full-duplex 10BASE-T
R/W R/W R/W R/W
Note 3 Note 3 Note 3 Note 3
4.4:0
Selector Field, S<4:0>
R/W
00001
1. R/W = Read/Write RO = Read Only 2. Default value of bit 4.10 is determined by pin 33/H8. 3. Default values of bits 4.5, 4.6, 4.7, and 4.8 are determined by LED/CFGn pins at reset. Refer to Table 8 for details.
Datasheet
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LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
Table 42. Auto Negotiation Link Partner Base Page Ability Register (Address 5)
Bit 5.15 Name Next Page Description 1 = Link Partner has ability to send multiple pages. 0 = Link Partner has no ability to send multiple pages. 1 = Link Partner has received Link Code Word from LXT972A. 0 = Link Partner has not received Link Code Word from the LXT972A. 1 = Remote fault. 0 = No remote fault. Ignore. Pause operation defined in Clause 40 and 27. 1 = Link Partner is Pause capable. 0 = Link Partner is not Pause capable. 1 = Link Partner is Pause capable. 0 = Link Partner is not Pause capable. 1 = Link Partner is 100BASE-T4 capable. 0 = Link Partner is not 100BASE-T4 capable. 1 = Link Partner is 100BASE-TX full-duplex capable. 0 = Link Partner is not 100BASE-TX full-duplex capable. 1 = Link Partner is 100BASE-TX capable. 0 = Link Partner is not 100BASE-TX capable. 1 = Link Partner is 10BASE-T full-duplex capable. 0 = Link Partner is not 10BASE-T full-duplex capable. 1 = Link Partner is 10BASE-T capable. 0 = Link Partner is not 10BASE-T capable. <00001> = IEEE 802.3. <00010> = IEEE 802.9 ISLAN-16T. <00000> = Reserved for future Auto-Negotiation development. <11111> = Reserved for future Auto-Negotiation development. Unspecified or reserved combinations shall not be transmitted. RO N/A Type 1 RO Default N/A
5.14
Acknowledge
RO
N/A
5.13 5.12 5.11
Remote Fault Reserved Asymmetric Pause Pause 100BASE-T4 100BASE-TX full-duplex 100BASE-TX 10BASE-T full-duplex 10BASE-T
RO RO
N/A N/A
5.10 5.9 5.8 5.7 5.6 5.5
RO RO RO RO RO RO
N/A N/A N/A N/A N/A N/A
5.4:0
Selector Field S<4:0>
RO
N/A
1. RO = Read Only
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Datasheet
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet -- LXT972A
Table 43. Auto Negotiation Expansion (Address 6)
Bit 6.15:6 Name Reserved Ignore on read. This bit indicates the status of the Auto-Negotiation variable, base page. It flags synchronization with the Auto-Negotiation state diagram allowing detection of interrupted links. This bit is only used if bit 16.1 (Alternate NP feature) is set. 1 = basepage = true 0 = basepage = false 6.4 6.3 6.2 Parallel Detection Fault Link Partner Next Page Able Next Page Able 1 = Parallel detection fault has occurred. 0 = Parallel detection fault has not occurred. 1 = Link partner is next page able. 0 = Link partner is not next page able. 1 = Local device is next page able. 0 = Local device is not next page able. 1 = Indicates that a new page has been received and the received code word has been loaded into register 5 (base pages) or register 8 (next pages) as specified in clause 28 of 802.3. This bit is cleared on read. If bit 16.1 is set, the Page Received bit is also cleared when mr_page_rx = false or transmit_disable = true. 1 = Link partner is auto-negotiation able. 0 = Link partner is not auto-negotiation able. RO/ LH RO RO 0 0 1 Description Type 1 RO Default 0
6.5
Base Page
RO/ LH
0
6.1
Page Received
RO LH
0
6.0
Link Partner A/ N Able
RO
0
1. RO = Read Only LH = Latching High
Table 44. Auto Negotiation Next Page Transmit Register (Address 7)
Bit 7.15 7.14 7.13 7.12 Name Next Page (NP) Reserved Message Page (MP) Acknowledge 2 (ACK2) Toggle (T) Message/ Unformatted Code Field Description 1 = Additional next pages follow 0 = Last page Write as 0, ignore on read 1 = Message page 0 = Unformatted page 1 = Complies with message 0 = Can not comply with message 1 = Previous value of the transmitted Link Code Word equalled logic zero 0 = Previous value of the transmitted Link Code Word equalled logic one Type 1 R/W RO R/W R/W Default 0 0 1 0
7.11
R/W
0
7.10:0
R/W
00000000 001
1. RO = Read Only. R/W = Read/Write
Datasheet
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LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
Table 45. Auto Negotiation Link Partner Next Page Receive Register (Address 8)
Bit 8.15 8.14 8.13 8.12 Name Next Page (NP) Acknowledge (ACK) Message Page (MP) Acknowledge 2 (ACK2) Toggle (T) Message/ Unformatted Code Field Description 1 = Link Partner has additional next pages to send 0 = Link Partner has no additional next pages to send 1 = Link Partner has received Link Code Word from LXT972A 0 = Link Partner has not received Link Code Word from LXT972A 1 = Page sent by the Link Partner is a Message Page 0 = Page sent by the Link Partner is an Unformatted Page 1 = Link Partner complies with the message 0 = Link Partner can not comply with the message 1 = Previous value of the transmitted Link Code Word equalled logic zero 0 = Previous value of the transmitted Link Code Word equalled logic one User definable Type 1 RO RO RO RO Default 0 0 0 0
8.11
RO
0
8.10:0
RO
0
1. RO = Read Only.
Table 46. Configuration Register (Address 16, Hex 10)
Bit 16.15 16.14 16.13 16.12 16.11 16.10 16.9 16.8 16.7 16.6 16.5 16.4:3 Name Reserved Force Link Pass Description Write as zero, ignore on read. 1 = Force Link pass 0 = Normal operation 1 = Disable Twisted Pair transmitter 0 = Normal Operation 1 = Bypass Scrambler and Descrambler 0 = Normal Operation Ignore 1 = Disable Jabber Correction 0 = Normal operation 1 = Enable Heart Beat 0 = Disable Heart Beat 1 = Disable TP loopback during half-duplex operation 0 = Normal Operation 1 = CRS deassert extends to RX_DV deassert 0 = Normal Operation Write as zero, ignore on read. Preamble Enable. PRE_EN Reserved 0 = Set RX_DV high coincident with SFD. 1 = Set RX_DV high and RXD = preamble when CRS is asserted. Write as zero, ignore on read. R/W R/W 0 00 Type 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 1 0
Transmit Disable Bypass Scrambler (100BASE-TX) Reserved Jabber (10BASE-T) SQE (10BASE-T) TP Loopback (10BASE-T) CRS Select (10BASE-T) Reserved
1. R/W = Read /Write, LHR = Latches High on Reset
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Datasheet
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet -- LXT972A
Table 46. Configuration Register (Address 16, Hex 10) (Continued)
Bit 16.2 16.1 16.0 Name Reserved Alternate NP feature Reserved Description Write as zero, ignore on read. 1 = Enable alternate auto negotiate next page feature. 0 = Disable alternate auto negotiate next page feature Write as zero, ignore on read. Type 1 R/W R/W R/W Default 0 0 0
1. R/W = Read /Write, LHR = Latches High on Reset
Table 47. Status Register #2 (Address 17)
Bit 17.15 17.14 17.13 17.12 17.11 17.10 17.9 17.8 Name Reserved 10/100 Mode Transmit Status Receive Status Collision Status Link Duplex Mode Auto-Negotiation Always 0. 1 = LXT972A is operating in 100BASE-TX mode. 0 = LXT972A is not operating 100BASE-TX mode. 1 = LXT972A is transmitting a packet. 0 = LXT972A is not transmitting a packet. 1 = LXT972A is receiving a packet. 0 = LXT972A is not receiving a packet. 1 = Collision is occurring. 0 = No collision. 1 = Link is up. 0 = Link is down. 1 = Full-duplex. 0 = Half-duplex. 1 = LXT972A is in Auto-Negotiation Mode. 0 = LXT972A is in manual mode. 1 = Auto-negotiation process completed. 0 = Auto-negotiation process not completed. This bit is only valid when auto negotiate is enabled, and is equivalent to bit 1.5. Reserved. 1 = Polarity is reversed. 0 = Polarity is not reversed. 1 = Device Pause capable. 0 = Device Not Pause capable. 1 = Error Occurred (Remote Fault, X,Y,Z). 0 = No error occurred. Always 0. Always 0. Always 0. Description Type 1 RO RO RO RO RO RO RO RO Default 0 0 0 0 0 0 0 0
17.7
Auto-Negotiation Complete Reserved Polarity Pause Error Reserved Reserved Reserved
RO
0
17.6 17.5 17.4 17:3 17:2 17:1 17.0
RO RO RO RO RO RO RO
0 0 0 0 0 0 0
1. RO = Read Only. R/W = Read/Write
Datasheet
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LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
Table 48. Interrupt Enable Register (Address 18)
Bit 18.15:9 18.8 18.7 Name Reserved Reserved ANMSK Write as 0; ignore on read. Write as 0; ignore on read. Mask for Auto Negotiate Complete 1 = Enable event to cause interrupt. 0 = Do not allow event to cause interrupt. Mask for Speed Interrupt 18.6 SPEEDMSK 1 = Enable event to cause interrupt. 0 = Do not allow event to cause interrupt. Mask for Duplex Interrupt 18.5 DUPLEXMSK 1 = Enable event to cause interrupt. 0 = Do not allow event to cause interrupt. Mask for Link Status Interrupt 18.4 18.3 18.2 18.1 18.0 LINKMSK Reserved Reserved INTEN TINT 1 = Enable event to cause interrupt. 0 = Do not allow event to cause interrupt. Write as 0, ignore on read. Write as 0, ignore on read. 1 = Enable interrupts. 0 = Disable interrupts. 1 = Force interrupt on MDINT. 0 = Normal operation. R/W R/W R/W R/W R/W 0 0 0 0 0 R/W 0 R/W 0 R/W 0 Description Type 1 R/W R/W Default N/A 0
1. R/W = Read /Write
Table 49. Interrupt Status Register (Address 19, Hex 13)
Bit 19.15:9 19.8 Name Reserved Reserved Ignore Ignore Auto Negotiation Status 19.7 ANDONE 1 = Auto Negotiation has completed. 0 = Auto Negotiation has not completed. Speed Change Status 19.6 SPEEDCHG 1 = A Speed Change has occurred since last reading this register. 0 = A Speed Change has not occurred since last reading this register. Duplex Change Status 19.5 DUPLEXCHG 1 = A Duplex Change has occurred since last reading this register. 0 = A Duplex Change has not occurred since last reading this register. Link Status Change Status 19.4 19.3 LINKCHG Reserved 1 = A Link Change has occurred since last reading this register. 0 = A Link Change has not occurred since last reading this register. Ignore RO 0 RO/SC 0 RO/SC 0 RO/SC 0 RO/SC N/A Description Type 1 RO RO Default N/A 0
1. R/W = Read/Write, SC = Self Clearing.
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Datasheet
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet -- LXT972A
Table 49. Interrupt Status Register (Address 19, Hex 13) (Continued)
Bit 19.2 19.1 19.0 Name MDINT Reserved Reserved 1 = MII interrupt pending. 0 = No MII interrupt pending. Ignore. Ignore Description Type 1 RO RO RO N/A 0 Default
1. R/W = Read/Write, SC = Self Clearing.
Datasheet
67
LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
Table 50. LED Configuration Register (Address 20, Hex 14)
Bit Name Description 0000 = Display Speed Status (Continuous, Default) 0001 = Display Transmit Status (Stretched) 0010 = Display Receive Status (Stretched) 0011 = Display Collision Status (Stretched) 0100 = Display Link Status (Continuous) 0101 = Display Duplex Status (Continuous) 0110 = Unused 0111 = Display Receive or Transmit Activity (Stretched) 1000 = Test mode- turn LED on (Continuous) 1001 = Test mode- turn LED off (Continuous) 1010 = Test mode- blink LED fast (Continuous) 1011 = Test mode- blink LED slow (Continuous) 1100 = Display Link and Receive Status combined 2 (Stretched)3 1101 = Display Link and Activity Status combined 2 (Stretched)3 1110 = Display Duplex and Collision Status combined 4 (Stretched)3 1111 = Unused 0000 = Display Speed Status 0001 = Display Transmit Status 0010 = Display Receive Status 0011 = Display Collision Status 0100 = Display Link Status (Default) 0101 = Display Duplex Status 0110 = Unused 0111 = Display Receive or Transmit Activity 1000 = Test mode- turn LED on 1001 = Test mode- turn LED off 1010 = Test mode- blink LED fast 1011 = Test mode- blink LED slow 1100 = Display Link and Receive Status combined 2 (Stretched)3 1101 = Display Link and Activity Status combined 2 (Stretched)3 1110 = Display Duplex and Collision Status combined 4 (Stretched)3 1111 = Unused 0000 = Display Speed Status 0001 = Display Transmit Status 0010 = Display Receive Status (Default) 0011 = Display Collision Status 0100 = Display Link Status 0101 = Display Duplex Status 0110 = Unused 0111 = Display Receive or Transmit Activity 1000 = Test mode- turn LED on 1001 = Test mode- turn LED off 1010 = Test mode- blink LED fast 1011 = Test mode- blink LED slow 1100 = Display Link and Receive Status combined 2 (Stretched)3 1101 = Display Link and Activity Status combined 2 (Stretched)3 1110 = Display Duplex and Collision Status combined 4 (Stretched)3 1111 = Unused Type 1 Default
LED1 20.15:12 Programming bits
R/W
0000
LED2 20.11:8 Programming bits
R/W
0100
LED3 20.7:4 Programming bits
R/W
0010
1. R/W = Read /Write RO = Read Only LH = Latching High 2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up. The secondary LED driver (Receive or Activity) causes the LED to change state (blink). 3. Combined event LED settings are not affected by Pulse Stretch bit 20.1. These display settings are stretched regardless of the value of 20.1. 4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full duplex. Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs. 5. Values are relative approximations. Not guaranteed or production tested.
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Datasheet
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet -- LXT972A
Table 50. LED Configuration Register (Address 20, Hex 14) (Continued)
Bit Name Description 00 = Stretch LED events to 30 ms. 01 = Stretch LED events to 60 ms. 10 = Stretch LED events to 100 ms. 11 = Reserved. 0 = Disable pulse stretching of all LEDs. 1 = Enable pulse stretching of all LEDs. Ignore. Type 1 Default
20.3:2
LEDFREQ
5
R/W
00
20.1 20.0
PULSESTRETCH Reserved
R/W R/W
1 N/A
1. R/W = Read /Write RO = Read Only LH = Latching High 2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up. The secondary LED driver (Receive or Activity) causes the LED to change state (blink). 3. Combined event LED settings are not affected by Pulse Stretch bit 20.1. These display settings are stretched regardless of the value of 20.1. 4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full duplex. Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs. 5. Values are relative approximations. Not guaranteed or production tested.
Table 51. Transmit Control Register #2 (Address 30)
Bit 30.15:11 30.12 Name Reserved Transmit Low Power Ignore 1 = Forces the transmitter into low power mode. Also forces a zero-differential transmission. 0 = Normal transmission. Port Rise Time Control1 00 = 2.7 ns (default is pins TXSLEW<1:0>) 01 = 3.5 ns 10 = 2.3 ns 11 = 2.0 ns Ignore R/W 0 Description Type2 R/W Default 0
30.11:10
R/W
N/A
30.9:0
Reserved
R/W
0
1. Values are relative approximations. Not guaranteed or production tested. 2. R/W = Read/Write
Datasheet
69
LXT972A -- 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
7.0
Package Specification
Figure 37. LXT972A LQFP Package Specifications
64-Pin Low Profile Quad Flat Pack
* Part Number - LXT972ALC Commercial Temperature Range (0C to +70C)
D
Millimeters Dim Min A A1 A2 B D D1 E E1 e L L1 - 0.05 1.35 0.17 11.85 9.9 11.85 9.9 Max 1.60 0.15 1.45 0.27 12.15 10.1 12.15 10.1
D1
E1
E
0.50 BSC1 0.45 0.75
1.00 REF 11
o
3
13o 7o
0o
e e/ 2
1. Basic Spacing between Centers
L1 A A1 L B
3 A2 3
70
Datasheet

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